Yield implications of wafer edge engineering

Kenneth Roy Harris; Boon Yong Ang

doi:10.1117/12.404862

23 October 2000 Yield implications of wafer edge engineering

Kenneth Roy Harris, Boon Yong Ang

Proceedings Volume 4229, Microelectronic Yield, Reliability, and Advanced Packaging; (2000) https://doi.org/10.1117/12.404862
Event: International Symposium on Microelectronics and Assembly, 2000, Singapore, Singapore

Abstract

Many uncharacterized phenomena occur at the edge of the wafer. Interactions between film stresses, tool clamp rings, lithography edge exclusions, etch non-uniformities, and CMP non-uniformities are some of the factors that influence the properties of the film stack close to the edge of the wafer. This paper discusses and provides examples of factors that should be considered when characterizing the film stack at the edge of the wafer. Tool interactions, edge exclusions, process non-uniformities, and other porcess variations are presented in this context. A relevant edge-engineering problem is then presented, where a delaminating film at the edge of the wafer contaminated the interior of the wafer. The solution to this problem involved a thorough characterization and redesign of the wafer edge film stacks. The discussion, analysis, and solution of this problem encompass and demonstrate the concepts reviewed in the paper.

Citation Download Citation

Kenneth Roy Harris and Boon Yong Ang "Yield implications of wafer edge engineering", Proc. SPIE 4229, Microelectronic Yield, Reliability, and Advanced Packaging, (23 October 2000); https://doi.org/10.1117/12.404862

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