Layout techniques for VLSI yield enhancement

Zhan Chen; Lixin Zhang

doi:10.1117/12.444666

15 October 2001 Layout techniques for VLSI yield enhancement

Zhan Chen, Lixin Zhang

Proceedings Volume 4600, Advances in Microelectronic Device Technology; (2001) https://doi.org/10.1117/12.444666
Event: International Symposium on Optoelectonics and Microelectronics, 2001, Nanjing, China

Abstract

Advances in semiconductor technology allow the manufacture of VLSI circuits with millions of transistors. With the increase in chip size and the decrease in layout feature size, yield loss due to manufacturing defects has become a serious problem. To overcome this problem, various defect-tolerant techniques have been developed to reduce the design sensitivity to manufacturing defects. This paper reviews techniques for yield enhancement in compaction, routing, and floorplanning stages of layout design.

Citation Download Citation

Zhan Chen and Lixin Zhang "Layout techniques for VLSI yield enhancement", Proc. SPIE 4600, Advances in Microelectronic Device Technology, (15 October 2001); https://doi.org/10.1117/12.444666

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