Modeling of passive components in VLSI technologies

Javier Sieiro; Jose Maria Lopez-Villegas; Jose Cabanillas

doi:10.1117/12.608743

30 June 2005 Modeling of passive components in VLSI technologies

Javier Sieiro, Jose Maria Lopez-Villegas, Jose Cabanillas

Proceedings Volume 5837, VLSI Circuits and Systems II; (2005) https://doi.org/10.1117/12.608743
Event: Microtechnologies for the New Millennium 2005, 2005, Sevilla, Spain

Abstract

On-chip passives, such as inductors, transformers, are key components in the design of RF building blocks when using VLSI technologies. Most of the time of the design cycle is used in the simulation of passives, trying to obtain the maximum performance. Recently, work on modelling of passives has been directed to pursuit fast computation algorithms due to the need to handle several passives in a complete RF circuit. However, small attention has been paid in the optimization of passives. The work presented tries to fill this gap. The algorithm is based on three steps: the split of the magnetic and electric modelling problem based in a PEEC description; a model order reduction, based on plausible arguments; and the use of analytical formulae to keep scalability. Fast computation is achieved thanks to both the separation of the magnetic and electric problem, and the model order reduction. By keeping an analytical formulation, the optimization of the layout for minimum losses is driven by a physical algorithm, instead of a mathematical one. The tool has been checked with experimental data from inductors fabricated in different VLSI technologies, showing its possibilities in the design of RF building blocks.

Citation Download Citation

Javier Sieiro, Jose Maria Lopez-Villegas, and Jose Cabanillas "Modeling of passive components in VLSI technologies", Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); https://doi.org/10.1117/12.608743

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