System-on-chip architecture with media DSP and RISC core for media application

Peng Liu

doi:10.1117/12.643258

10 February 2006 System-on-chip architecture with media DSP and RISC core for media application

Peng Liu

Proceedings Volume 6074, Multimedia on Mobile Devices II; 60740D (2006) https://doi.org/10.1117/12.643258
Event: Electronic Imaging 2006, 2006, San Jose, California, United States

Abstract

Systems-on-chips provide single-chip solutions in many embedded applications to meet the applications size and power requirements. Media processing such as real-time compression and decompression of video signal is now expected to be the driving force in the evolution of media processor. The MediaSoC322xA consists of two fully programmable processor cores and integrates digital video encoder. The programmable cores toward a particular class of algorithms: the MediaDSP3200 for RISC/DSP oriented functions and multimedia processing, and the RISC3200 for bit stream processing and control function. Dedicated interface units for DRAM, SDRAM, Flash, SRAM, on screen display and the digital video encoder are connected via a 32-bit system bus with the processor cores. The MediaSoC322xA is fabricated in a 0.18um 6LM standard-cell SMIC CMOS technology, occupies about 20mm², and operates at 180MHz. The MeidaSoC322xA are used to audio/video decoder for embedded multimedia application.

Citation Download Citation

Peng Liu "System-on-chip architecture with media DSP and RISC core for media application", Proc. SPIE 6074, Multimedia on Mobile Devices II, 60740D (10 February 2006); https://doi.org/10.1117/12.643258

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