Paper
23 May 2007 A design tool for high-resolution high-frequency cascade continuous-time ΣΔ modulators
Author Affiliations +
Proceedings Volume 6590, VLSI Circuits and Systems III; 659016 (2007) https://doi.org/10.1117/12.721896
Event: Microtechnologies for the New Millennium, 2007, Maspalomas, Gran Canaria, Spain
Abstract
This paper introduces a CAD methodology to assist the designer in the implementation of continuous-time (CT) cascade ΣΔ modulators. The salient features of this methodology are: (a) flexible behavioral modeling for optimum accuracy-efficiency trade-offs at different stages of the top-down synthesis process; (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity; and (c) mixed knowledge-based and optimization-based architectural exploration and specification transmission for enhanced circuit performance. The applicability of this methodology will be illustrated via the design of a 12 bit 20 MHz CT ΣΔ modulator in a 1.2V 130nm CMOS technology.
© (2007) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
R. Tortosa, R. Castro-López, J. M. de la Rosa, A. Rodríguez-Vázquez, and F. V. Fernández "A design tool for high-resolution high-frequency cascade continuous-time ΣΔ modulators", Proc. SPIE 6590, VLSI Circuits and Systems III, 659016 (23 May 2007); https://doi.org/10.1117/12.721896
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KEYWORDS
Modulators

Computer aided design

Signal to noise ratio

Optimization (mathematics)

Logic

Performance modeling

Amplifiers

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