Inter-pixel capacitance in fully-depleted silicon hybrid CMOS focal plane arrays

Yibin Bai; Mark C. Farris; Anders K. Petersen; James W. Beletic

doi:10.1117/12.739787

17 September 2007 Inter-pixel capacitance in fully depleted silicon hybrid CMOS focal plane arrays

Yibin Bai, Mark C. Farris, Anders K. Petersen, James W. Beletic

Proceedings Volume 6690, Focal Plane Arrays for Space Telescopes III; 669004 (2007) https://doi.org/10.1117/12.739787
Event: Optical Engineering + Applications, 2007, San Diego, California, United States

Abstract

Inter-Pixel capacitance (IPC) is an effect that can occur in bump-bonded hybrid CMOS pixel arrays that employ a source follower pixel amplifier. IPC can result in the signal in one pixel being sensed by adjacent pixels that are capacitively coupled. IPC effect is more pronounced in full-depletion silicon hybrid CMOS focal plane arrays than infrared arrays because of the stronger coupling path through the silicon detector layer. IPC can degrade the image resolution and it can cause an overestimation of conversion gain (electrons per mV) determined from conventional photon-transfer method because the IPC "blur" reduces the variance of photon noise. However, the IPC effect can be minimized with improvements in pixel design, and the conversion gain can be properly calculated, and image resolution can be restored with deconvolution techniques. In this paper, we report the results of a recent effort to reduce IPC in Teledyne's visible silicon hybrid CMOS focal plane arrays through pixel design improvements.

Citation Download Citation

Yibin Bai, Mark C. Farris, Anders K. Petersen, and James W. Beletic "Inter-pixel capacitance in fully depleted silicon hybrid CMOS focal plane arrays", Proc. SPIE 6690, Focal Plane Arrays for Space Telescopes III, 669004 (17 September 2007); https://doi.org/10.1117/12.739787

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