Paper
23 March 1986 Signal Processing Applications Of 70 Mhz Bit-Serial Hardware
Richard W. Linderman
Author Affiliations +
Abstract
This paper examines signal processing applications of high speed bit-serial arithmetic and control circuitry which has been designed and tested for performance in the 50 MHz to 100 MHz range. A dense layout technique allows as many as 70 28-bit serial multipliers to be placed on a single 1.25 micron CMOS chip. At 70 MHz, this provides a throughput of 144 million multiplications per second. Applications to Fourier transform processors, digital filters, and matrix multi-plication are presented as examples. The bit-serial hardware is shown to have several advantages over bit-parallel alternatives.
© (1986) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Richard W. Linderman "Signal Processing Applications Of 70 Mhz Bit-Serial Hardware", Proc. SPIE 0698, Real-Time Signal Processing IX, (23 March 1986); https://doi.org/10.1117/12.976252
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Signal processing

Clocks

Digital signal processing

Logic

Very large scale integration

Laser processing

Tolerancing

RELATED CONTENT

A 4 GHz digital receiver using the Uniboard platform
Proceedings of SPIE (September 24 2012)
Special Purpose Devices For Signal And Image Processing An...
Proceedings of SPIE (December 24 1980)
Comparison Between Two Kinds Of Digital Signal Processor
Proceedings of SPIE (January 01 1987)
Rethinking image registration on customizable hardware
Proceedings of SPIE (August 27 2010)
FFT on reconfigurable hardware
Proceedings of SPIE (September 19 1995)

Back to Top