Circuit-topology driven OPC for increased performance/yield ratio

Edmund Pierzchala; Fedor Pikus; J. Andres Torres

doi:10.1117/12.814367

12 March 2009 Circuit-topology driven OPC for increased performance/yield ratio

Edmund Pierzchala, Fedor Pikus, J. Andres Torres

Proceedings Volume 7275, Design for Manufacturability through Design-Process Integration III; 72751A (2009) https://doi.org/10.1117/12.814367
Event: SPIE Advanced Lithography, 2009, San Jose, California, United States

Abstract

A circuit-topology-driven approach to Optical Proximity Correction (OPC) is presented. By tailoring device critical dimension (CD) statistical distribution to the device function in the circuit, and ensuring that the CD distribution stays within the correct (possibly variable) limits during process maturation and other process changes, it can be an effective tool for optimizing circuit's performance/yield tradeoff in high-volume manufacturing. Calibre's proprietary Programmable Electrical Rule Checks (PERC) module is used to recognize the topology. Alternatively, an external static timing tool can be used to identify critical devices.

Citation Download Citation

Edmund Pierzchala, Fedor Pikus, and J. Andres Torres "Circuit-topology driven OPC for increased performance/yield ratio", Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72751A (12 March 2009); https://doi.org/10.1117/12.814367

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