Paper
5 May 2010 Toward wafer-scale fabrication and 3D integration of micro-solid oxide fuel cells for portable energy
Bo-Kuai Lai, Alex C. Johnson, Masaru Tsuchiya, Shriram Ramanathan
Author Affiliations +
Abstract
Pathways to scaling up the power and voltage output of on-chip micro-solid oxide fuel cells (μSOFC) have been investigated. μSOFC arrays consisting of one thousand three hundred and thirty-two (1332) membranes have been lithographically fabricated on 4" wafers. The membranes, with widths of ~150 μm, are comprised of 15-nm-thick La0.6Sr0.4Co0.8F0.2O3 (LSCF) or 100-nm-thick porous Pt cathodes, 75-nm-thick Y0.15Z0.85O1.93 (YSZ) electrolytes, and 100-nm-thick porous Pt anodes. Yield of fabrication is greater than 99% and only a few membranes failed after annealing at 500 °C. However, to reduce resistive loss, a current collector or a much thicker LSCF needs to be implemented if using LSCF as the cathode material on 4" wafers. Prototype components of μSOFC stacks for scaling up output voltage are also presented. The stacks require only two components - namely, a μSOFC plate and a bipolar separator - to form a repeating unit for the stacks. Flow channels and through silicon vias are integrated in the components. Challenges in fabrication and direction for further improvement for these approaches are discussed. The preliminary results suggest potential for further exploration into wafer-scale processing of fuel cell device structures for portable energy.
© (2010) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Bo-Kuai Lai, Alex C. Johnson, Masaru Tsuchiya, and Shriram Ramanathan "Toward wafer-scale fabrication and 3D integration of micro-solid oxide fuel cells for portable energy", Proc. SPIE 7679, Micro- and Nanotechnology Sensors, Systems, and Applications II, 767916 (5 May 2010); https://doi.org/10.1117/12.846916
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KEYWORDS
Silicon

Semiconducting wafers

Platinum

Etching

Oxides

Prototyping

Annealing

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