A hardware implementation of nonlinear correlation filters

Saúl Martínez-Díaz; Hugo Castañeda-Girón

doi:10.1117/12.892433

24 September 2011 A hardware implementation of nonlinear correlation filters

Saúl Martínez-Díaz, Hugo Castañeda-Girón

Proceedings Volume 8135, Applications of Digital Image Processing XXXIV; 81351D (2011) https://doi.org/10.1117/12.892433
Event: SPIE Optical Engineering + Applications, 2011, San Diego, California, United States

Abstract

Recently, nonlinear correlation filters have been proposed for distortion-invariant pattern recognition. The design of the filters is based on rank-order, logical operations and nonlinear correlation. These kinds of filters are robust to non Gaussian noise and non-homogeneous illumination. A drawback of nonlinear filters is its high computational cost; however, the computation of nonlinear correlation can be parallelized. In this paper a hardware implementation of nonlinear filtering is presented. The hardware coprocessor is based on a Field Programmable Gate Array (FPGA) device. Simulation results are provided and discussed.

Citation Download Citation

Saúl Martínez-Díaz and Hugo Castañeda-Girón "A hardware implementation of nonlinear correlation filters", Proc. SPIE 8135, Applications of Digital Image Processing XXXIV, 81351D (24 September 2011); https://doi.org/10.1117/12.892433

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