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Modern space missions are becoming increasingly complex: the interconnection of the units in a satellite is now a network
of terminals linked together through routers, where devices with different level of automation and intelligence share the
same data-network.
The traceability of the network transactions is performed mostly at terminal level through log analysis and hence it is
difficult to verify in real time the reliability of the interconnections and the interchange protocols. To improve and ease the
traffic analysis in a SpaceWire network we implemented a low-level link analyzer, with the specific goal to simplify the
integration and test phases in the development of space instrumentation. The traffic analyzer collects signals coming from
pod probes connected in-series on the interested links between two SpaceWire terminals. With respect to the standard
traffic analyzers, the design of this new tool includes the possibility to internally reshape the LVDS signal. This
improvement increases the robustness of the analyzer towards environmental noise effects and guarantees a deterministic
delay on all analyzed signals.
The analyzer core is implemented on a Xilinx FPGA, programmed to decode the bidirectional LVDS signals at Link and
Network level. Successively, the core packetizes protocol characters in homogeneous sets of time ordered events. The
analyzer provides time-tagging functionality for each characters set, with a precision down to the FPGA Clock, i.e. about
20nsec in the adopted HW environment. The use of a common time reference for each character stream allows synchronous
performance measurements. The collected information is then routed to an external computer for quick analysis: this is
done via high-speed USB2 connection.
With this analyzer it is possible to verify the link performances in terms of induced delays in the transmitted signals. A
case study focused on the analysis of the Time-Code synchronization in presence of a SpaceWire Router is shown in this
paper as well.
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