Mk x Nk gated CMOS imager

James Janesick; Tom Elliott; James Andrews; John Tower; Perry Bell; Alan Teruya; Joe Kimbrough; Jeanne Bishop

doi:10.1117/12.2063524

10 September 2014 Mk x Nk gated CMOS imager

James Janesick, Tom Elliott, James Andrews, John Tower, Perry Bell, Alan Teruya, Joe Kimbrough, Jeanne Bishop

Proceedings Volume 9211, Target Diagnostics Physics and Engineering for Inertial Confinement Fusion III; 921106 (2014) https://doi.org/10.1117/12.2063524
Event: SPIE Optical Engineering + Applications, 2014, San Diego, California, United States

Abstract

Our paper will describe a recently designed Mk x Nk x 10 um pixel CMOS gated imager intended to be first employed at the LLNL National Ignition Facility (NIF). Fabrication involves stitching MxN 1024x1024x10 um pixel blocks together into a monolithic imager (where M = 1, 2, . .10 and N = 1, 2, . . 10). The imager has been designed for either NMOS or PMOS pixel fabrication using a base 0.18 um/3.3V CMOS process. Details behind the design are discussed with emphasis on a custom global reset feature which erases the imager of unwanted charge in ~1 us during the fusion ignition process followed by an exposure to obtain useful data. Performance data generated by prototype imagers designed similar to the Mk x Nk sensor is presented.

Citation Download Citation

James Janesick, Tom Elliott, James Andrews, John Tower, Perry Bell, Alan Teruya, Joe Kimbrough, and Jeanne Bishop "Mk x Nk gated CMOS imager", Proc. SPIE 9211, Target Diagnostics Physics and Engineering for Inertial Confinement Fusion III, 921106 (10 September 2014); https://doi.org/10.1117/12.2063524

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