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When CMOS technology reaches 28/20nm node and beyond, several new schemes are implemented such as High K metal gate (HKMG) which can enhance the device performance and has better control of device current leakage. Dummy poly gate removal (DPGR) process is introduced for HKMG, and works as a key process to control the work function of metal gate and threshold voltage (Vt) shift. In dry etch technology, conventional continuous wave (CW) plasma process has been widely used, however, it may not be capable for some challenging process in 28nm node and beyond. In DPGR process for HKMG scheme, CW scheme may result in plasma damage of gate oxide/capping layer for its inherent high electron temperature (Te) and ion energy while synchronous pulsing scheme is capable to simultaneously pulse both source and bias power, which could achieve lower Te, independent control of ion and radical flux, well control the loading of polymer deposition on dense/ isolate features. It’s the first attempt to utilize synchronous pulsing plasma in DPGR process. Experiment results indicate that synchronous pulsing could provide less silicon recess under thin gate oxide which is induced by the plasma oxidation. Furthermore, the loading of HK capping layer loss between long channel and short channel can be well controlled which plays a key role on transistor performance, such as leakage and threshold voltage shift. Additionally, it has been found that synchronous pulsing could distinctly improve ILD loss when compared with CW, which is helpful to broaden the whole process window.
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