Impact of EUV patterning scenario on different design styles and their ground rules for 7nm/5nm node BEOL layers

Tsann-Bim Chiou; Alek C. Chen; Mircea Dusa; Shih-En Tseng

doi:10.1117/12.2220019

16 March 2016 Impact of EUV patterning scenario on different design styles and their ground rules for 7nm/5nm node BEOL layers

Tsann-Bim Chiou, Alek C. Chen, Mircea Dusa, Shih-En Tseng

Author Affiliations +

Proceedings Volume 9781, Design-Process-Technology Co-optimization for Manufacturability X; 978107 (2016) https://doi.org/10.1117/12.2220019
Event: SPIE Advanced Lithography, 2016, San Jose, California, United States

Abstract

As the IC industry moves forward to 7nm or 5nm node, the minimum pitch of back-end-of-line (BEOL) layers could be near 30nm. Extreme ultraviolet (EUV) could be the most cost effective solution for patterning critical metal and via layers. Patterning of the critical layers would need greater than 4x exposures using ArFi lithography, leading to severe cost and yield issues. There are two potential design options, one-dimension (1D) and two-dimension (2D), for metal 1 layer. EUV’s single exposure option offers superior image quality especially for the 2D design style, but scalability of a 2D design is limited by EUV with a fixed numerical aperture (NA). The single exposure of EUV is an appropriate patterning solution for printing a 1D design directly, but maintaining critical dimension uniformity (CDU) of lines and line-ends is a challenge. Scalability of the 1D design is also limited by the single exposure option. The 1D design can be patterned through a spacer film deposition to gain superior line CD control, followed by printing a cut or block pattern to create the line-ends. Since the minimum pitch of cut/block patterns is generally larger than the metal pitch, EUV’s single exposure option has a potential to print the cut/block pattern at smaller pitch and resolution and offers an opportunity to further design shrink. An elongated via design helps design scalability due to an insensitive overlay error contribution to via-to-metal contact area and encroachment.

Citation Download Citation

Tsann-Bim Chiou, Alek C. Chen, Mircea Dusa, and Shih-En Tseng "Impact of EUV patterning scenario on different design styles and their ground rules for 7nm/5nm node BEOL layers", Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 978107 (16 March 2016); https://doi.org/10.1117/12.2220019

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