Noise optimization of the source follower of a CMOS pixel using BSIM3 noise model

Swaraj Mahato; Guy Meynants; Gert Raskin; J. De Ridder; H. Van Winckel

doi:10.1117/12.2231190

27 July 2016 Noise optimization of the source follower of a CMOS pixel using BSIM3 noise model

Swaraj Mahato, Guy Meynants, Gert Raskin, J. De Ridder, H. Van Winckel

Proceedings Volume 9915, High Energy, Optical, and Infrared Detectors for Astronomy VII; 99151P (2016) https://doi.org/10.1117/12.2231190
Event: SPIE Astronomical Telescopes + Instrumentation, 2016, Edinburgh, United Kingdom

Abstract

CMOS imagers are becoming increasingly popular in astronomy. A very low noise level is required to observe extremely faint targets and to get high-precision flux measurements. Although CMOS technology offers many advantages over CCDs, a major bottleneck is still the read noise. To move from an industrial CMOS sensor to one suitable for scientific applications, an improved design that optimizes the noise level is essential. Here, we study the 1/f and thermal noise performance of the source follower (SF) of a CMOS pixel in detail. We identify the relevant design parameters, and analytically study their impact on the noise level using the BSIM3v3 noise model with an enhanced model of gate capacitance. Our detailed analysis shows that the dependence of the 1/f noise on the geometrical size of the source follower is not limited to minimum channel length, compared to the classical approach to achieve the minimum 1/f noise. We derive the optimal gate dimensions (the width and the length) of the source follower that minimize the 1/f noise, and validate our results using numerical simulations. By considering the thermal noise or white noise along with 1/f noise, the total input noise of the source follower depends on the capacitor ratio C_G/C_FD and the drain current (Id). Here, C_G is the total gate capacitance of the source follower and C_FD is the total floating diffusion capacitor at the input of the source follower. We demonstrate that the optimum gate capacitance (C_G) depends on the chosen bias current but ranges from C_FD/3 to C_FD to achieve the minimum total noise of the source follower. Numerical calculation and circuit simulation with 180nm CMOS technology are performed to validate our results.

Citation Download Citation

Swaraj Mahato, Guy Meynants, Gert Raskin, J. De Ridder, and H. Van Winckel "Noise optimization of the source follower of a CMOS pixel using BSIM3 noise model", Proc. SPIE 9915, High Energy, Optical, and Infrared Detectors for Astronomy VII, 99151P (27 July 2016); https://doi.org/10.1117/12.2231190

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KEYWORDS

Capacitance

Capacitors

Cadmium sulfide

CMOS sensors

CMOS technology

Field effect transistors

Transistors

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