Advanced Packaging and its associated technology blocks (such as hybrid bonding, BackSide Power Delivery Networks, wafer reconstruction, die embedding etc) are becoming key enablers for extending Moore’s Law and scaling in general. Given that there are multiple application spaces utilising Advanced Packaging e.g. High Performance Computing, Chiplets, wafer level packaging etc the challenges facing Lithography cover the full range of illumination wavelength approaches plus Scan & Repeat, Direct Write and Imprint Lithography. Within this presentation we will discuss the Advanced Packaging landscape, putting into context various technology blocks such as through wafer high resolution patterning, Fine Pitch Redistribution Layer (FP-RDL) patterning, through die patterning of embedded die, Chiplet options and all with respect to resolution, overlay options plus some discussion on secondary issues such as die level defectivity and distortion. We conclude with a consolidated interconnect pitch roadmap clarifying basic interconnect options.
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