Presentation + Paper
28 March 2017 The use of computational inspection to identify process window limiting hotspots and predict sub-15nm defects with high capture rate
Boo-Hyun Ham, Il-Hwan Kim, Sung-Sik Park, Sun-Young Yeo, Sang-Jin Kim, Dong-Woon Park, Joon-Soo Park, Chang-Hoon Ryu, Bo-Kyeong Son, Kyung-Bae Hwang, Jae-Min Shin, Jangho Shin, Ki-Yeop Park, Sean Park, Lei Liu, Ming-Chun Tien, Angelique Nachtwein, Marinus Jochemsen, Philip Yan, Vincent Hu, Christopher Jones
Author Affiliations +
Abstract
As critical dimensions for advanced two dimensional (2D) DUV patterning continue to shrink, the exact process window becomes increasingly difficult to determine. The defect size criteria shrink with the patterning critical dimensions and are well below the resolution of current optical inspection tools. As a result, it is more challenging for traditional bright field inspection tools to accurately discover the hotspots that define the process window. In this study, we use a novel computational inspection method to identify the depth-of-focus limiting features of a 10 nm node mask with 2D metal structures (single exposure) and compare the results to those obtained with a traditional process windows qualification (PWQ) method based on utilizing a focus modulated wafer and bright field inspection (BFI) to detect hotspot defects. The method is extended to litho-etch litho-etch (LELE) on a different test vehicle to show that overlay related bridging hotspots also can be identified.
Conference Presentation
© (2017) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Boo-Hyun Ham, Il-Hwan Kim, Sung-Sik Park, Sun-Young Yeo, Sang-Jin Kim, Dong-Woon Park, Joon-Soo Park, Chang-Hoon Ryu, Bo-Kyeong Son, Kyung-Bae Hwang, Jae-Min Shin, Jangho Shin, Ki-Yeop Park, Sean Park, Lei Liu, Ming-Chun Tien, Angelique Nachtwein, Marinus Jochemsen, Philip Yan, Vincent Hu, and Christopher Jones "The use of computational inspection to identify process window limiting hotspots and predict sub-15nm defects with high capture rate", Proc. SPIE 10145, Metrology, Inspection, and Process Control for Microlithography XXXI, 101451P (28 March 2017); https://doi.org/10.1117/12.2257964
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KEYWORDS
Inspection

Semiconducting wafers

Metrology

Scanning electron microscopy

Critical dimension metrology

Electron beam lithography

Metals

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