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6 June 2024 Design of lightweight memory protection solution based on RISC-V processor
Kai Nie, Rongcai Zhao, Xiao Zhang, Shuyu Li
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Proceedings Volume 13175, International Conference on Computer Network Security and Software Engineering (CNSSE 2024); 131751Q (2024) https://doi.org/10.1117/12.3032024
Event: 4th International Conference on Computer Network Security and Software Engineering (CNSSE 2024), 2024, Sanya, China
Abstract
With the rapid advancement of modern processor technologies, the potential threat to processor memory security from external devices necessitates robust memory protection mechanisms. To ensure the stability and security of processors, Input-Output (IO) physical memory protection mechanisms are commonly employed to prevent unauthorized access to processor memory. However, the redundancy in the mapping relationships between modules in traditional IO physical memory protection mechanisms leads to an increase in processor runtime. This paper, focusing on RISC-V processors, presents an efficient memory protection scheme, named L-OPT, by investigating traditional IO physical memory protection approaches. L-OPT optimizes the mapping relationships between internal modules in conventional memory protection schemes. In comparison with the unoptimized state of the processor in memory testing scenarios, L-OPT demonstrates a 112% efficiency improvement, validating its effectiveness in enhancing processor runtime efficiency.
(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.
Citation Download Citation
Kai Nie, Rongcai Zhao, Xiao Zhang, and Shuyu Li "Design of lightweight memory protection solution based on RISC-V processor", Proc. SPIE 13175, International Conference on Computer Network Security and Software Engineering (CNSSE 2024), 131751Q (6 June 2024); https://doi.org/10.1117/12.3032024
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KEYWORDS
Design
Computer security
Mendelevium
Inspection
Computing systems
Design rules
Information operations
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