With the rapid advancement of modern processor technologies, the potential threat to processor memory security from external devices necessitates robust memory protection mechanisms. To ensure the stability and security of processors, Input-Output (IO) physical memory protection mechanisms are commonly employed to prevent unauthorized access to processor memory. However, the redundancy in the mapping relationships between modules in traditional IO physical memory protection mechanisms leads to an increase in processor runtime. This paper, focusing on RISC-V processors, presents an efficient memory protection scheme, named L-OPT, by investigating traditional IO physical memory protection approaches. L-OPT optimizes the mapping relationships between internal modules in conventional memory protection schemes. In comparison with the unoptimized state of the processor in memory testing scenarios, L-OPT demonstrates a 112% efficiency improvement, validating its effectiveness in enhancing processor runtime efficiency.
Cache isolation is a highly effective method for defending against cache side-channel attacks. This approach divides the cache into different isolation domains, assigning distinct domains to mutually untrusted processes, preventing processes from sharing the cache across domains. However, existing solutions have certain limitations. Cache partitioning based on ways has a limited number of isolation domains and may not fully meet users' practical needs. Page coloring schemes require proportional allocation of memory and cache, which is inflexible. This paper introduces ICS, a flexible and secure cache isolation solution. ICS supports up to hundreds of isolation domains, with memory allocation independent of the cache. Additionally, domain management is convenient. ICS is a set isolation solution, with its core being SMT. SMT modifies the mapping relationship between memory and LLC, directing the memory of different isolation domains to distinct cache sets. Implemented with a 1MB 16-way LLC, ICS can support a maximum of 512 isolation domains, with a storage overhead of approximately 1.3% and performance loss of around 1%. It represents a cost-effective method for defending against cache side-channel attacks.
KEYWORDS: Open source software, Computer simulations, Computer architecture, Signal generators, Information technology, Field programmable gate arrays, Design and modelling, Clocks, Power consumption, Signal processing
Interrupt technology is a key technology for processors to respond to external events and plays an important role in the embedded field. The open source RISC-V architecture defines a complete set of interrupt mechanisms with hardware definitions that do not support interrupt nesting in embedded systems that only support machine mode, and software support for interrupt nesting adds additional time overhead. This paper is based on the interrupt mechanism defined by RISC-V, using a state machine to control the global interrupt enablement of the processor to support interrupt nesting, and to save the site and restore the site through hardware stacking and out-stacking to avoid the time consumption caused by the software level; a dedicated entry point for interrupt service program jumps further speeds up the response. In this paper, we design and implement a fast interrupt system using Hummingbird E203, an open source kernel defined by standard RISC-V, as an experimental platform. Simulation verification and comprehensive implementation on FPGA platform show that compared to the interrupt handling process of Hummingbird E203, using a small amount of hardware resource consumption, the response speed is improved by 1/4, providing better real-time performance and flexibility in embedded applications.
KEYWORDS: Power consumption, Design and modelling, Matrices, Convolutional neural networks, Windows, Clocks, Computer architecture, Convolution, Image compression, Digital signal processing
A low-power RISC-V-based convolutional neural network acceleration processor is proposed to cope with the problem that the increasing resource requirements of convolutional neural networks in the direction of hardware convolutional acceleration are difficult to be met on embedded devices. The processor is designed with three instructions that can configure the parameters of each CNN layer to accommodate different input data, multiplex computational resources to reduce power consumption, and execute operations that repeat a large number of executions in parallel to speed up operation efficiency. Through comparison experiments, it can be found that this processor acceleration instruction set is 20.93 times, 7.67 times, and 8.97 times faster than the base RISC-V instruction set after verified with the same data on three operations, including convolution, activation, and pooling, respectively. The experimental results show that the total power consumption of the processor with this custom instruction set is only 0.221 W at 16 MHZ operating frequency, which is advantageous in terms of performance-to-power ratio compared to other RISC-V accelerated processors with less resource consumption and lower power consumption.
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