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Upcoming generations of integrated circuits (e.g., below the 2nm device node) will be achieved with the help of anamorphic optics in High-NA EUV scanners which cause the effective exposure field of the High-NA scanner to be scaled in half compared to its Low-NA EUV and DUV counterparts. Therefore, layers exposed on High-NA anamorphic scanners will require two or more stitched mask exposures to achieve the equivalent exposure area of previous-generation scanners. The lithography patterning at a stitching boundary between two mask exposures will be affected by additional process variation such as exposure-to-exposure overlay/dose/focus offsets and mask-to-mask overlay/mask-CD offsets. Therefore, the allowed patterns printed at a stitching boundary must be restricted relative to patterns printed at single exposure regions on the wafer. The physical design flow of the chip must be aware of the stitching region and optimized to be stitching-friendly. Fortunately, there are a variety of different options for designing stitch-friendly target patterns and for optimization of stitched patterns in OPC/RET. In this paper we will review and test different improvement options for enabling High-NA stitch-friendly design and patterning.
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Kevin Lucas, Zachary Levinson, Yunqiang Zhang, Xiangyu Zhou, Kevin Hooker, Linghui Wu, Lin Wang, Michael Lam, Soo-Han Choi, James Ban, "Design and process-friendly High-NA EUV stitching options," Proc. SPIE 13216, Photomask Technology 2024, 132161U (12 November 2024); https://doi.org/10.1117/12.3034869