CMOS compatibiltity of high-aspect-ratio micromachining (HARM) in bonded silicon-on-insulator (BSOI)

Mark E. McNie; David O. King

doi:10.1117/12.324311

31 August 1998 CMOS compatibiltity of high-aspect-ratio micromachining (HARM) in bonded silicon-on-insulator (BSOI)

Mark E. McNie, David O. King

Proceedings Volume 3511, Micromachining and Microfabrication Process Technology IV; (1998) https://doi.org/10.1117/12.324311
Event: Micromachining and Microfabrication, 1998, Santa Clara, CA, United States

Abstract

In this paper, we review work on a novel low temperature SOI HARM process at the Defence Evaluation and Research Agency (DERA) and its integration with on-chip CMOS electronics -- as part of a fully integrated MEMS process or as 'value-added' post-processing on commercial CMOS wafers. BSOI material was designed for micromachining applications. The SOI layer acted as a device layer while the insulating dielectric acted as an etch stop and as a sacrificial layer. This resulted in a low stress material that was optimized for the sacrificial release process. Trench isolation was achieved by deep dry etching to the buried dielectric. These trenches could be refilled to allow metallization to reach isolated components. Higher temperature refill material could also act as a lateral mechanical anchor for structures that would otherwise be completely undercut and float off during the sacrificial process. Structures with aspect ratios of up to 50:1 have been defined using combinations of photolithography, deposition and dry etching. CMOS transistor and capacitor characteristics were measured before and after SOI HARM processing. No detectable change in their characteristics was found. This process is attractive for many micromachining applications. Prototype micro-inertial devices fabricated in this technology are also presented in this paper.

Citation Download Citation

Mark E. McNie and David O. King "CMOS compatibiltity of high-aspect-ratio micromachining (HARM) in bonded silicon-on-insulator (BSOI)", Proc. SPIE 3511, Micromachining and Microfabrication Process Technology IV, (31 August 1998); https://doi.org/10.1117/12.324311

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available