Digital-readout CMOS design for capacitive sensors using on-chip variable sense capacitor arrays

Ashok Srivastava; Hanson Yong; Daniel Wildhaber; Mohammed Hasan; Vishnupriya Gongalreddy; Jing Wang; Pratul K. Ajmera; Farzad Pouralborz

doi:10.1117/12.354284

20 July 1999 Digital-readout CMOS design for capacitive sensors using on-chip variable sense capacitor arrays

Ashok Srivastava, Hanson Yong, Daniel Wildhaber, Mohammed Hasan, Vishnupriya Gongalreddy, Jing Wang, Pratul K. Ajmera, Farzad Pouralborz

Author Affiliations +

Proceedings Volume 3673, Smart Structures and Materials 1999: Smart Electronics and MEMS; (1999) https://doi.org/10.1117/12.354284
Event: 1999 Symposium on Smart Structures and Materials, 1999, Newport Beach, CA, United States

Abstract

A digital readout design in CMOS technology is described for monolithic integration with microelectromechanical capacitive sensors using on-chip variable sense capacitor arrays with resolutions of 2.5 fF, 10 fF and 40 fF, respectively. The designed circuit produces a 4-bit digital readout proportional to the capacitive difference between the sense and the reference capacitors. The CMOS digital readout is compatible with +/- 1.5 V operation for low power consumption, uses a +1.5 V reference voltage with a switching speed of approximately 100 kHz. The digital readout design presented here is quite general and can be used in a wide variety of analog microsensors on the chip.

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Ashok Srivastava, Hanson Yong, Daniel Wildhaber, Mohammed Hasan, Vishnupriya Gongalreddy, Jing Wang, Pratul K. Ajmera, and Farzad Pouralborz "Digital-readout CMOS design for capacitive sensors using on-chip variable sense capacitor arrays", Proc. SPIE 3673, Smart Structures and Materials 1999: Smart Electronics and MEMS, (20 July 1999); https://doi.org/10.1117/12.354284

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