Hybrid pipelined and multiplexed FIR filter architecture

Waqas Akram; Earl E. Swartzlander Jr.

doi:10.1117/12.406509

13 November 2000 Hybrid pipelined and multiplexed FIR filter architecture

Waqas Akram, Earl E. Swartzlander Jr.

Proceedings Volume 4116, Advanced Signal Processing Algorithms, Architectures, and Implementations X; (2000) https://doi.org/10.1117/12.406509
Event: International Symposium on Optical Science and Technology, 2000, San Diego, CA, United States

Abstract

This paper presents a hybrid pipelined and multiplexed architecture for finite-duration impulse response (FIR) filters used in real- time applications. The emphasis is placed on efficient hardware utilization, compared to conventional multiplexed or pipelined architectures. The multiply-accumulate (MAC) unit used here is a Booth recoded, Wallace tree based multiplier, in which the accumulator is merged with the partial product matrix. However, the approach is equally well suited to other multiplier/accumulator implementations. A novel sign extension technique is described and incorporated into the partial product reduction phase. This effectively reduces the number of rows that need sign extension, and can be used in conjunction with existing sign extension techniques. The final structure described is a form of pipelined tap-division multiplexing with the goal of maximum hardware re-use during run-time, given input data rate constraints. A method to compute the optimal hybrid pipeline depth is presented, based on the ratio of the input data rate to the critical speed of the hardware in the target technology. Performance is measured against FIR structures implemented using conventional, multiplexed, and pipelined approaches. It is shown that hardware complexity reductions of up to 18% over conventional pipelined architectures, and up to 29% over multiplexed approaches can be achieved.

Citation Download Citation

Waqas Akram and Earl E. Swartzlander Jr. "Hybrid pipelined and multiplexed FIR filter architecture", Proc. SPIE 4116, Advanced Signal Processing Algorithms, Architectures, and Implementations X, (13 November 2000); https://doi.org/10.1117/12.406509

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KEYWORDS

Multiplexing

Finite impulse response filters

Optical filters

Filtering (signal processing)

Logic

Clocks

Computer architecture

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