Parallel image compression circuit for high-speed cameras

Yukinari Nishikawa; Shoji Kawahito; Toru Inoue

doi:10.1117/12.588030

25 February 2005 Parallel image compression circuit for high-speed cameras

Yukinari Nishikawa, Shoji Kawahito, Toru Inoue

Proceedings Volume 5671, Real-Time Imaging IX; (2005) https://doi.org/10.1117/12.588030
Event: Electronic Imaging 2005, 2005, San Jose, California, United States

Abstract

In this paper, we propose 32 parallel image compression circuits for high-speed cameras. The proposed compression circuits are based on a 4 x 4-point 2-dimensional DCT using a DA method, zigzag scanning of 4 blocks of the 2-D DCT coefficients and a 1-dimensional Huffman coding. The compression engine is designed with FPGAs, and the hardware complexity is compared with JPEG algorithm. It is found that the proposed compression circuits require much less hardware, leading to a compact high-speed implementation of the image compression circuits using parallel processing architecture. The PSNR of the reconstructed image using the proposed encoding method is better than that of JPEG at the region of low compression ratio.

Citation Download Citation

Yukinari Nishikawa, Shoji Kawahito, and Toru Inoue "Parallel image compression circuit for high-speed cameras", Proc. SPIE 5671, Real-Time Imaging IX, (25 February 2005); https://doi.org/10.1117/12.588030

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