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Approaches to verify post-OPC designs for manufacturing have evolved from a number of separate inspection strategies. OPC decorations are verified by design rule or optical rule checkers, the reticle is verified by a reticle inspection system, and the patterned wafers are verified by wafer inspection and metrology tools. Each verification step looks at a different representation of the desired device pattern with very little data flowing between them.
Previously, we reported a new paradigm in design verification, moving the OPC verification from the design plane to the wafer plane where it really matters. The DesignScanTM system inspects the OPC decorated design by simulating how the design will be transferred to the reticle layer and how that reticle will be imaged into resist across the full focus-exposure calibration window, which can be up to twice as large as the process window. DesignScanTM first simulates the resist images at the nominal conditions (the best focus/exposure-F0E0) and compares them to pre-OPC design to detect unacceptable variations. Then it simulates resist images across the focus-exposure window and compares them to the best focus/exposure reference. Defect detection algorithms are applied to determine if any unacceptable variation in the pattern occurs within the nominal process window.
In this paper we will propose a new methodology on process window monitoring for OPC databases using DesignScan and report results for a chip. We will also report newly developed 2D defect detectors: line end shortening (LES) and interlayer overlap (ILO). New applications will be discussed and reported; such as, determination of the reticle target CD specification through process window simulation across a range of target CDs by biasing the post-OPC data by a few nanometers in both directions (+ and -). Pattern dependent reticle CD specifications are possible by identifying the weak structures.
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