Mask parameter variation in the context of the overall variation budget of an advanced logic wafer Fab

Rolf Seltmann; Gert Burbach; Anne Parge; Jens Busch; Tino Hertzsch; Andre Poock; Francois Weisbuch; Andre Holfeld

doi:10.1117/12.835166

27 May 2009 Mask parameter variation in the context of the overall variation budget of an advanced logic wafer fab

Rolf Seltmann, Gert Burbach, Anne Parge, Jens Busch, Tino Hertzsch, Andre Poock, Francois Weisbuch, Andre Holfeld

Proceedings Volume 7470, 25th European Mask and Lithography Conference; 747006 (2009) https://doi.org/10.1117/12.835166
Event: 25th European Mask and Lithography Conference, 2009, Dresden, Germany

Abstract

Within our paper we are going to discuss the variation within the patterning process in the context of the overall electrical parameter variation in an advanced logic Fab. The evaluation is based on both the variation of ring oscillators that are distributed across the chip as well as on local variation of matched transistor pairs. Starting with a view back to the 130nm technology, we will show how things and requirements changed over time. In particular we focus on the gate layer where we do a detailed ACLV-comparison from the 130nm technology node down to today's 45nm node. Within the patterning variation we keep special attention on the mask performance. Within that section, we do a detailed wafer-mask correlation analysis. Additionally to the low-MEEF gate layer we show the importance of the mask CD-performance for a typical high MEEF-layer. Finally, we discuss the mask contribution to the overall overlay error for the most critical contact to gate overlay. In all of the cases, we will show that the mask performance is not the limiter within today's most advanced technology, as long as we get access to a world class mask shop.

Citation Download Citation

Rolf Seltmann, Gert Burbach, Anne Parge, Jens Busch, Tino Hertzsch, Andre Poock, Francois Weisbuch, and Andre Holfeld "Mask parameter variation in the context of the overall variation budget of an advanced logic wafer fab", Proc. SPIE 7470, 25th European Mask and Lithography Conference, 747006 (27 May 2009); https://doi.org/10.1117/12.835166

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KEYWORDS

Photomasks

Semiconducting wafers

Optical lithography

Etching

Transistors

Line width roughness

Logic

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