High-speed optical correlator with custom electronics interface design

Tien-Hsin Chao; Thomas T. Lu

doi:10.1117/12.2018262

29 April 2013 High-speed optical correlator with custom electronics interface design

Tien-Hsin Chao, Thomas T. Lu

Proceedings Volume 8748, Optical Pattern Recognition XXIV; 874803 (2013) https://doi.org/10.1117/12.2018262
Event: SPIE Defense, Security, and Sensing, 2013, Baltimore, Maryland, United States

Abstract

Jet Propulsion Laboratory has developed an innovative Grayscale Optical Correlator (GOC) architecture using a pair of Digital Light Processor Spatial Light Modulator (DLP SLM) as the input and filter devices and a CMOS sensor for correlation output detection [1-5]. In order to achieve ultra high-speed Automatic Target Recognition (ATR), we have developed custom Electronic Interfaces to maximize the system data throughput rate for both the DLP and CMOS. The high-performance Electronic Interface System (EIS) is capable of achieving sustained 1000 frames per second (fps) at 1920x1024 data frame size. In this paper, we will first overview the new GOC architecture. We will the depict the detailed design of the EIS for the DLP SLM and CMOS. The innovation of JPL’s high-performance digital/optical ATR system is in its implementation of a high-speed, high-resolution DLP display, and a high-speed CMOS camera sensor with an advanced I/O interface and high-speed parallel on-board processing capability.

Citation Download Citation

Tien-Hsin Chao and Thomas T. Lu "High-speed optical correlator with custom electronics interface design", Proc. SPIE 8748, Optical Pattern Recognition XXIV, 874803 (29 April 2013); https://doi.org/10.1117/12.2018262

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