We present the first experimental demonstration of a neuromorphic network with magnetic tunnel junction (MTJ) synapses, which performs image recognition via vector-matrix multiplication. We also simulate a large MTJ network performing MNIST handwritten digit recognition, demonstrating that MTJ crossbars can match memristor accuracy while providing increased precision, stability, and endurance.
We present initial experimental results and simulate a nanomagnet reservoir computer (NMRC) solving tasks requiring high memory content, with an area-energy-delay product ten-million times lower than CMOS systems. We manufactured a small nanomagnet reservoir demonstrating a frustrated state. We evaluated the performance on two novel tasks. Our results indicate the reservoir’s short-term memory capabilities and ability to integrate information from multiple concurrent inputs. In the end, our system saw a reduction in area by a factor of 50,000, in energy by a factor of 60, and in period by a factor of four as compared with an equivalent CMOS reservoir.
Prevention of integrated circuit counterfeiting through logic locking faces the fundamental challenge of securing an obfuscation key against physical and algorithmic threats. Previous work has focused on strengthening the logic encryption to protect the key against algorithmic attacks but failed to provide adequate physical security. In this work, we propose a logic locking scheme that leverages the non-volatility of the nanomagnet logic (NML) family to achieve both physical and algorithmic security. Polymorphic NML minority gates protect the obfuscation key against algorithmic attacks, while a strain-inducing shield surrounding the nanomagnets provides physical security via a self-destruction mechanism, securing against invasive attacks. We experimentally demonstrate that shielded magnetic domains are indistinguishable, securing against imaging attacks. As NML suffers from low speeds, we propose a hybrid CMOS logic scheme with embedded obfuscated NML “islands”. The NML secures the functionality of sensitive logic while CMOS drives the timing-critical paths.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.