Interests: Technologies and applications for manufacture of thin film devices such as ICs, integrated optics, MEMS.
Managed Intel’s first Proteus OPC technology transfer to Shrink. Executed novel model-based design validation and process margin improvement. Met Shrink yield objectives on the 1st lot out accelerating technology qualification and conversion to Shrink of LOGIC products; a $100M gain.
Investigated resolution enhancement for microlithography. Invented and implemented an effective 2-D OPC using an e-test sized serif design, automated insertion and validation. Extended lithography process window, at yield and on POR process, from k1=1.0 to 0.5 achieving 4x lower transistor power. Sparked an industry-wide interest in OPC leading to decade of lithography extensions and explosive growth of CAD/EDA, mask making, inspection, and metrology.
After GCA alignment post-mortem, lead alignment- and overlay-related projects. As IBM consultant to step-and-scan JD with Perkin-Elmer characterized performance issues, modeled them, estimated errors. Established effective performance metrics, now standard. Built IBM TD infrastructure, a record of achievements and technology leadership. Influenced equipment vendors and consortia; industry-wide, 20x error reduction in 5 yrs. Co-developed SEM-based overlay metrology. Contributed overlay metrology content in SEMI standards and INTRS. VLSI Research: “forever changed overlay measurement requirements”.
Lead overlay development in IBM-Siemens-Toshiba DRAM alliance; eliminated "overlay control as a technology roadblock".
Invented effective dose and focus monitors for applications with optical metrology tools.
Managed Ultratech Alignment/Metrology Engineering. Supported Applications and strategic customers. Delivered wafer global and fine alignment in narrow scribe. Developed stepper self-metrology, accelerated improvement of alignment, column stability, and matching. Enabled new market penetration and system sales.
Managed Intel’s first Proteus OPC technology transfer to Shrink. Executed novel model-based design validation and process margin improvement. Met Shrink yield objectives on the 1st lot out accelerating technology qualification and conversion to Shrink of LOGIC products; a $100M gain.
Investigated resolution enhancement for microlithography. Invented and implemented an effective 2-D OPC using an e-test sized serif design, automated insertion and validation. Extended lithography process window, at yield and on POR process, from k1=1.0 to 0.5 achieving 4x lower transistor power. Sparked an industry-wide interest in OPC leading to decade of lithography extensions and explosive growth of CAD/EDA, mask making, inspection, and metrology.
After GCA alignment post-mortem, lead alignment- and overlay-related projects. As IBM consultant to step-and-scan JD with Perkin-Elmer characterized performance issues, modeled them, estimated errors. Established effective performance metrics, now standard. Built IBM TD infrastructure, a record of achievements and technology leadership. Influenced equipment vendors and consortia; industry-wide, 20x error reduction in 5 yrs. Co-developed SEM-based overlay metrology. Contributed overlay metrology content in SEMI standards and INTRS. VLSI Research: “forever changed overlay measurement requirements”.
Lead overlay development in IBM-Siemens-Toshiba DRAM alliance; eliminated "overlay control as a technology roadblock".
Invented effective dose and focus monitors for applications with optical metrology tools.
Managed Ultratech Alignment/Metrology Engineering. Supported Applications and strategic customers. Delivered wafer global and fine alignment in narrow scribe. Developed stepper self-metrology, accelerated improvement of alignment, column stability, and matching. Enabled new market penetration and system sales.
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