Historically LYNRED (created from the merger of SOFRADIR and ULIS in 2019) has used amorphous silicon materials (“a-Si”) as thermistor materials for its uncooled microbolometer products. If a-Si materials present several advantages that made the success of LYNRED’s products (easy to use and integrate in thermal camera), their intrinsic bolometric performances (i.e. TCR and 1/f noise) are still lower than the commonly used oxides thermistors[1] (i.e. VOx[2] and TiOx[3]). In order to stay in a leading position regarding sensor performances without any trade-off, LYNRED, with the support of its historical R&D partner the CEA-LETI, developed new materials. This strategy has led to new cutting edge products. At the end of 2020 a new 17 µm pixel pitch product (Pico640s[4]), with one of the highest sensor performance reported on the market (typical thermal sensitivity of 25 mK (f/1, 300K, 30Hz)), has been introduced in our product portfolio. We also launched our state of the art 12 µm product range with performances equivalent to our current 17µm product range. More generally, these developments open up new opportunities toward smaller pixel pitch. The symposium presentation and the associated article will present how we have increased the "Signal to Noise Ratio" (SNR) of our products while keeping all the elements which have been our hallmark. Special attention will be paid to NETD, stability of product characteristics during operation and manufacturing excellence. All these features were obtained only by hardware (at the pixel level) improvements without the need to use sophisticated algorithms or specific ROIC functions, in the spirit of LYNRED’s FPA products.
We report on the CMOS-compatible hybrid III-V/Silicon platform developed in CEA-LETI. In order to follow the large-scale integration capabilities of silicon photonics, already available worldwide in 200mm or 300mm through different foundries, the development of CMOS-compatible process for the III-V integration is of major interest. The technological developments involve not only the hybridization on top of a mature silicon photonic front-end wafer through direct molecular bonding but the patterning of the III-V epitaxy layer, low access resistance contacts, as well as planar multilevel BEOL must also be investigated and optimized. Test vehicles for the process validation based on either distributed feedback (DFB) or distributed Bragg reflector (DBR) laser cavities were designed. A modular approach is proposed in order to minimize the impact on the already qualified silicon photonics devices. Next, a collective III–V die bonding and processing have been successfully developed in this platform. The collective bonding, based on a flexible template holder, allows for large scale die to wafer transfer in both 200 and 300mm. After the III-V substrate removal and III-V patterning relying on optimized dry etching processes, CMOS compatible metallization’s are used to realize ohmic contact on n-InP and P-InGaAs leading to contact resistivity in the range of 10−6 Ω·cm². While first demonstrations have been obtained through wafer bonding, the fabrication process was subsequently validated on III-V dies bonding with a fabrication yield of Fabry-Perot lasers of 97% in 200mm. A planarized two-metal-level BEOL was used to connect the devices, leading to a drastic reduction of series resistance between 5.5 and 7 Ω. Finally, the functionality of DFB and DBR lasers is demonstrated with SMSR up to 50 dB and maximum output power of 3 mW in CW. The overall technological features are expected improve the efficiency, density, and cost of silicon photonics PICs.
Hybrid III-V/Si laser integration on silicon photonic platform has been demonstrated several time using III-V direct bonding on top of patterned silicon [1-3]. Most of these former works have been achieved using small wafer diameter III-V fabrication line for post bonding process steps. The expected low-cost added value of silicon photonics cannot be sustained with such integration scheme. More recently, we present III-V laser integration with a CMOS compatible process using wafer to wafer bonding and 1 level of contact [4]. In this paper, we present the technological progresses on a 200mm fully CMOS compatible hybrid III-V/Si laser technology. We introduced an improved backend of line for hybrid lasers with 2 interconnection levels, W-plugs and fully planarized process offering a state of the art access resistance and a homogeneous current density distribution over the gain material. Second, in order to optimize the use of the costly III-V material and enable the laser large scale integration on silicon we present fabrication process with die to wafer molecular bonding with high bonding yield at wafer scale. These process features will be detailed and the impact of laser performances will be presented. Finally, the scalability towards 300mm for the overall platform will be discussed.
Silicon photonic platforms are becoming more and more mature with competitive devices suitable for increasing needs of HPC (High Performance Computing) systems and datacenters. Compared to bulk III-V technologies, Si photonic technologies are suffering from the lack of integrated light source. Several works have been done in the past years to integrate laser on silicon using III-V direct bonding on top of patterned silicon. These demonstrations were using a CMOS compatible process for the silicon part but all the process steps following the introduction of the III-V material were done with small wafer diameter III-V fabrication lines. With such integrations, the cost advantage of silicon photonics based on the use of CMOS platforms and large wafer format is no more valid.
In this paper we present the integration of a hybrid III-V/Si laser using a fully CMOS compatible 200mm technology. The laser is integrated in a mature photonic platform. The additional process modules required for this integration will be deeply described. These modules are localized silicon thickening using damascene process, Bragg reflector patterning with DUV lithography, III-V patterning and ohmic contact formation with no lift-off and without noble metal. This integration is compatible with a multi metal levels planar BEOL, mandatory for photonic circuit design.
The first DFB lasers fabricated with this new platform are operating at 1310nm with a threshold current around 60mA, a SMSR larger than 45dB and more than 1.5mW optical power in the output waveguide. New laser designs, specifically adapted for this new process, will be introduced and fabricated.
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