A prototype of a readout IC (ROIC) designed for use in high temperature coefficient of resistance (TCR) SiGe microbolometers is presented. The prototype ROIC architecture implemented is based on a bridge with active and blind bolometer pixels with a capacitive transimpedance amplifier (CTIA) input stage and column parallel integration with serial readout. The ROIC is designed for use in high (≥ 4 %/K) TCR and high detector resistance Si/SiGe microbolometers with 17x17 μm2 pixel sizes in development. The prototype has been designed and fabricated in 0.25- μm SiGe:C BiCMOS process.
A 32x32 prototype of a digital readout IC (DROIC) for medium-wave infrared focal plane arrays (MWIR IR-FPAs) is presented. The DROIC employs in-pixel photocurrent to digital conversion based on a pulse frequency modulation (PFM) loop and boasts a novel feature of off-pixel residue conversion using 10-bit column SAR ADCs. The remaining charge at the end of integration in typical PFM based digital pixel sensors is usually wasted. Previous works employing in-pixel extended counting methods make use of extra memory and counters to convert this left-over charge to digital, thereby performing fine conversion of the incident photocurrent. This results in a low quantization noise and hence keeps the readout noise low. However, focal plane arrays (FPAs) with small pixel pitch are constrained in pixel area, which makes it difficult to benefit from in-pixel extended counting circuitry. Thus, in this work, a novel approach to measure the residue outside the pixel using column -parallel SAR ADCs has been proposed. Moreover, a modified version of the conventional PFM based pixel has been designed to help hold the residue charge and buffer it to the column ADC. In addition to the 2D array of pixels, the prototype consists of 32 SAR ADCs, a timing controller block and a memory block to buffer the residue data coming out of the ADCs. The prototype has been designed and fabricated in 90nm CMOS.
Digital pixels based on pulse frequency modulation (PFM) employ counting techniques to achieve very high charge
handling capability compared to their analog counterparts. Moreover, extended counting methods making use of leftover
charge (residue) on the integration capacitor help improve the noise performance of these pixels. However, medium
wave infrared (MWIR) focal plane arrays (FPAs) having smaller pixel pitch are constrained in terms of pixel area which
makes it difficult to add extended counting circuitry to the pixel. Thus, this paper investigates the performance of digital
pixels employing off-pixel residue measurement. A circuit prototype of such a pixel has been designed for 15μm pixel
pitch and fabricated in 90nm CMOS. The prototype is composed of a pixel front-end based on a PFM loop. The frontend
is a modified version of conventional design providing a means for buffering the signal that needs to be converted to
a digital value by an off-pixel ADC. The pixel has an integration phase and a residue measurement phase. Measured
integration performance of the pixel has been reported in this paper for various detector currents and integration times.
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