EUV lithography has been well-established over the past few years, to be the next technological milestone, to achieve lower pattern resolutions i.e. higher technology nodes. Ensuring a lower defect count however is particularly important for its use in mass-production, because of the considerably high cost of EUV masks. EUV wavelength (actinic EUV inspection) is necessary to be able to catch and characterize EUV defects correctly, particularly phase defects, originating due to imperfections in multi-layers. Defects on a patterned mask require EUV wavelengths (higher resolution) for accurate assessment of their CD impact. However, DUV optics are also employed by mask shops, along with SEM review, as a cost-effective option. Emphasizing the importance of defect handling in EUV masks, especially for EUV masks without pellicles in the memory industry, the most difficult part of EUV mask management is in controlling adder. Detecting smaller adder size is required as mask pattern size is getting smaller in higher technology nodes, which accompanies increased sensitivity of patterned mask inspection and unavoidable increase in noise signal that makes it hard to proper classify mask defects. This paper talks about the details of how DUV inspection optics are utilized to achieve an efficient pre-filtering of EUV mask defects. This, coupled with well-tested automatic defect classification algorithms of Calibre® DefectClassify, results in a reliable solution to manage regular classification of mask defects as real or false, under such sensitive conditions.
At the core of Design-technology co-optimization (DTCO) processes, is the Design Space Exploration (DSE), where different design schemes and patterns are systematically analyzed and design rules and processes are co-optimized for optimal yield and performance before real products are designed. Synthetic layout generation offers a solution. With rules-based synthetic layout generation, engineers design rules to generate realistic layout they will later see in real product designs. This paper shows two approaches to generating full coverage of the design space and providing contextual layout. One approach relies on Monte Carlo methods and the other depends on combining systematic and random methods to core patterns and their contextual layout. Also, in this paper we present a hierarchical classification system that catalogs layouts based on pattern commonality. The hierarchical classification is based on a novel algorithm of creating a genealogical tree of all the patterns in the design space.
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