Mr. Jaewoo Seo Profile

Jaewoo Seo

at SAMSUNG Electronics Co Ltd

SPIE Involvement:

Author

Publications (2)

This will count as one of your downloads.

You will have access to both the presentation and article (if available).

DOWNLOAD NOW

This content is available for download via your institution's subscription. To access this item, please sign in to your personal account.

Email or Username Forgot your username?

Password Forgot your password?

Show

Keep me signed in

No SPIE account? Create an account

Proceedings Article | 20 March 2018 Paper

A compact multi-bit flip-flop with smaller height implementation and metal-less intra-cell routing

Jaewoo Seo, Jinwook Jung, Youngsoo Shin

Proceedings Volume 10588, 105880A (2018) https://doi.org/10.1117/12.2297519

KEYWORDS: Clocks, Logic, Multiplexers, Metals, LCDs, Legal, Standards development, Electrical engineering, Electronics, Circuit switching

Read Abstract +

Multi-bit flip-ops (MBFFs) are widely used in modern circuit designs because of their lower power consumption and smaller footprint. However, conventional MBFFs have routability issues due to the dense intra-cell connections. Since many horizontal connections are populated in the typical MBFF layouts, metal-2 (M2) tracks are highly occupied inside the cell. Accordingly, routers cannot leverage the M2 tracks for inter-cell connections. The conventional MBFFs also show a limited impact on the cell area reduction. Since the cell area saving of an MBFF mainly comes from the clock driver sharing, the layouts of other ip-op modules remain almost the same. In this paper, we propose a compact MBFF with metal-less clock routing and smaller height implementation. To achieve a sparse population of M2 routing tracks, we vertically place MBFF modules and interconnect them using the poly layer. As a result, the wire length of M2 layer inside a cell is significantly reduced. We also propose the smaller cell height implementation for compact MBFF layouts. Assuming the default standard cell height of 9 tracks, we present a 6-track MBFF implementation and the glue logic which makes legal cell placement with the 9-track logic cells. Experiments with a few test circuits show that the number of routing grids having congestion overflow is reduced by 16% and 73%, on average, compared to the single-bit flip-op and conventional MBFF based designs, respectively. Total cell area is also reduced by 8% and 2%, on average, compared to the single-bit flip-op and conventional MBFF based designs, respectively.

Proceedings Article | 28 March 2017 Presentation + Paper

Routability enhancement through unidirectional standard cells with floating metal-2

Jaewoo Seo, Youngsoo Shin

Proceedings Volume 10148, 101480K (2017) https://doi.org/10.1117/12.2258010

KEYWORDS: 193nm lithography, Standards development, Optics manufacturing, Light sources, Manufacturing, Extreme ultraviolet, Microelectromechanical systems, Metals, Lithography, Capacitance

Read Abstract +

Bidirectional cell refers to a standard cell, in which metal-1 is used for both horizontal and vertical connections. Unidirectional cell, on the other hand, assumes reserved routing, e.g. metal-1 for only horizontal and metal-2 for only vertical connections. It has been introduced to take advantage of regular metal patterns, which are easier to print and can overcome the lithography limitations in sub-32nm technology. In unidirectional cell, metal-2 is laid out following the cell placement pitch. Since metal-2 pitch is usually different from placement pitch, some within-cell metal-2 become off track. This significantly degrades metal-2 routability. We propose a unidirectional cell with floating metal-2. After initial cell placement, metal-2 segment within each cell is snapped to nearest metal-2 track and is fixed. In addition, we propose cell redesign and post-placement optimization to enhance metal-1 routability. Metal-1 connections are forced to populate in limited number of tracks, so that remaining tracks are exposed during routing. Combined with post-placement optimization, this allows many longer metal-1 tracks to be available for horizontal connection. Experiments with test circuits show that routing errors are reduced by 7% and 60% with the proposed metal-1 considerations and floating metal-2 together.

My Library

You currently do not have any folders to save your paper to! Create a new folder below.

Folder Name

Folder Description

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks. You are receiving this notice because your organization may not have SPIE eBooks access.*

*Shibboleth/Open Athens users─please sign in to access your institution's subscriptions.

To obtain this item, you may purchase the complete book in print or electronic format on SPIE.org.

ORGANIZATIONAL
Sign in with credentials provided by your organization.

Organizational Username

Organizational Password

Show/Hide Password

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available

Members:

Non-members: ADD TO CART

Keywords/Phrases

Search In:

Publication Years