Patterning of contact hole using KrF lithography system for the sub 90nm technology node is one of the most
challenging tasks. Contact hole pattern can be printed using Off-Axis Illumination(OAI) such as dipole or Quasar or
Quadrupole at KrF lithography system. However this condition usually offer poor image contrast and poor Depth Of
Focus(DOF), especially isolated contact hole. Sub-resolution assist features (SRAF) have been shown to provide
significant process window enhancement and across chip CD variation reduction. The insertion of SRAF in a contact
design is mostly done using rule based scripting. However the rule based SRAF strategy that has been followed
historically is not always able to increase the process window of these 'forbidden pitches' sufficiently to allow
sustainable manufacturing. Especially in case of random contact hole, rule-based SRAF placement is almost impossible
task. We have used an inverse lithography technique to treat random contact hole.
In this paper we proved the impact of SRAF configuration. Inverse lithography technique was successfully used to treat
random contact holes. It is also shown that the experimental data are easily predicted by calibrating aerial image
simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described.
As a conclusion, we suggest methodology to set up optimum SRAF configuration with rule and inverse lithography
technology.
As IC design complexity keeps increasing, it is more and more difficult to ensure the pattern transfer after
optical proximity correction (OPC) due to the continuous reduction of layout dimensions and lithographic limitation by
k1 factor. To guarantee the imaging fidelity, resolution enhancement technologies (RET) such as off-axis illumination
(OAI), different types of phase shift masks and OPC technique have been developed. In case of model-based OPC, to
cross-confirm the contour image versus target layout, post-OPC verification solutions continuously keep developed -
contour generation method and matching it to target structure, method for filtering and sorting the patterns to eliminate
false errors and duplicate patterns. The way to detect only real errors by excluding false errors is the most important
thing for accurate and fast verification process - to save not only reviewing time and engineer resource, but also whole
wafer process time and so on. In general case of post-OPC verification for metal-contact/via coverage (CC) check,
verification solution outputs huge of errors due to borderless design, so it is too difficult to review and correct all points
of them. It should make OPC engineer to miss the real defect, and may it cause the delay time to market, at least.
In this paper, we studied method for increasing efficiency of post-OPC verification, especially for the case of
CC check. For metal layers, final CD after etch process shows various CD bias, which depends on distance with
neighbor patterns, so it is more reasonable that consider final metal shape to confirm the contact/via coverage. Through
the optimization of biasing rule for different pitches and shapes of metal lines, we could get more accurate and efficient
verification results and decrease the time for review to find real errors. In this paper, the suggestion in order to increase
efficiency of OPC verification process by using simple biasing rule to metal layout instead of etch model application is
presented.
Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm
technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI)
such as Quasar or Quadrupole. However, such a source usually offers poor image contrast and poor depth of focus
(DOF), especially for isolated contact holes. In addition to image contrast and DOF, circularity of hole shape is also an
important parameter for device performance. Sub-resolution assist features (SRAF) can be used to improve the image
contrast, DOF and circularity for isolated contact holes. Application of SRAFs, modifies the intensity profile of isolated
features to be more like dense ones, improving the focal response of the isolated feature. The insertion of SRAFs in a
contact design is most commonly done using rule-based scripting, where the initial rules for configuring the SRAFs are
derived using a simulation tool to determining the distance of assist features to main feature, and the size and number of
assist features to be used. However in the case of random contact holes, rule-based SRAF placement is a nearly
impossible task.
To address this problem, an inverse lithography technique was successfully used to treat random contact holes. The
impact of SRAF configuration on pattern profile, especially circularity and process margin, is demonstrated. It is also
shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a
methodology for optimizing SRAF rules using inverse lithography technology is described.
Design For Manufacturing (DFM) has become an important focusing part in the semiconductor
industry as the feature size on the chip goes down below the 0.13um technology. Lots of DFM related ideas
have been come up, tried, and adopted for wider process window and higher device performance. As the
minimum features are getting shrunk, the design rules also become more complicated, but still not good
enough to describe the certain pattern that imposes narrow process window or even failure of device. Thus,
these process hot spot patterns become to identify, correct, or remove at the design step. One of the efforts is
to support a DFM guide line to the designer or add to conventional DRC rules. However it is very difficult to
make DFM guideline because we detect the hot spot pattern and confirm if these patterns is real hot spot or
not.
In this study, we developed effective methodology how to make DFM guide line. Firstly we use the s
oftware, called nanoscope to detect hot spots on post OPC layouts and then make this detected hot spot patter
n to test patterns that it can check electrical performance and then we compared with electrical performance a
ccording to split condition. It is confirmed this method is very effective to make DFM guide line below the 0.
13um technology.
Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm
technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI)
such as Quasar or Quadrupole. However, such a source usually offers poor image contrast and poor depth of focus
(DOF), especially for isolated contact holes. In addition to image contrast and DOF, circularity of hole shape is also an
important parameter for device performance. Sub-resolution assist features (SRAF) can be used to improve the image
contrast, DOF and circularity for isolated contact holes. Application of SRAFs, modifies the intensity profile of isolated
features to be more like dense ones, improving the focal response of the isolated feature. The insertion of SRAFs in a
contact design is most commonly done using rule-based scripting, where the initial rules for configuring the SRAFs are
derived using a simulation tool to determining the distance of assist features to main feature, and the size and number of
assist features to be used.. However in the case of random contact holes, rule-based SRAF placement is a nearly
impossible task.
To address this problem, an inverse lithography technique was successfully used to treat random contact holes. The
impact of SRAF configuration on pattern profile, especially circularity and process margin, is demonstrated. It is also
shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a
methodology for optimizing SRAF rules using inverse lithography technology is described.
As integrated circuit technology advances and features shrink, the scale of critical dimension (CD) variations induced by
lithography effects become comparable with the critical dimension of the design itself. At the same time, each
technology node requires tighter margins for errors introduced in the lithography process. Optical and process models --
the black boxes that simulate the pattern transfer onto silicon -- are becoming more and more concerned with those
different process errors. As a consequence, an optical proximity correction (OPC) model consists mainly of two parts; a
physical part dealing with the physics of light and its behavior through the lithographical patterning process, and an
empirical part to account for any process errors that might be introduced between writing the mask and sampling
measurements of patterns on wafer. Understanding how such errors can affect a model's stability and predictability, and
taking such errors into consideration while building a model, could actually help convergence, stability, and
predictability of the model when it comes to design patterns other than those used during model calibration and
verification. This paper explores one method to quickly enhance model accuracy and stability.
As devices size move toward 90nm technology node or below, defining uniform bit line CD of flash devices is one of
the most challenging features to print in KrF lithography. There are two principal difficulties in defining bit line on wafer.
One is insufficient process margin besides poor resolution compared with ArF lithography. The other is that asymmetric
bit line should be made for OPC(Optical Proximity Correction) modeling. Therefore advanced ArF lithography scanner
should be used for define bit line with RETs (Resolution Enhancement Techniques) such as immersion lithography, OPC,
PSM(Phase Shift Mask), high NA(Numerical Aperture), OAI(Off-Axis Illumination), SRAF(Sub-resolution Assistant
Feature), and mask biasing.. Like this, ArF lithography propose the method of enhancing resolution, however, we must
spend an enormous amount of CoC(cost of ownership) to utilize ArF photolithography process than KrF.
In this paper, we suggest method to improve of bit line CD uniformity, patterned by KrF lithographic process in 90nm
sFlash(stand alone Flash) devices. We applied new scheme of mask manufacturing, which is able to realize 2 different
types of mask, binary and phase-shift, into one plate. Finally, we could get the more uniform bit lines and we expect to
get more stable properties then before applying this technique.
It has been widely accepted that to ensure good yield in IC wafer manufacturing, early adaptation of DFM (Design for
Manufacturability) guidelines in design phase is required and it is particularly true in Foundry business. Integrated
foundry approaches for DFM guideline development were presented in this paper. With emphasis of process variations
and process sensitivity impact on design patterns, we describe the procedure of the combination of rule-based and
simulation-based lithographical hotspot pattern characterizations. An evaluation of process sensitivity metrics for
analyzing potential pattern hotspots is then described. In addition, based on hotspot pattern severity, repeated patterns
from different designs are saved into a pattern library as knowledge deposition tool and those patterns can be easily
identified later in new designs through pattern search, which is much faster than simulation based hotspot detections.
With this approach, a set of DFM compliance rules is derived to designs in the design implementation stage for both
110nm and 90nm technology nodes, striving to gain more yield, device performance, and improve time-to-volume
production.
Foundry companies encounter again and again the same or similar lithography unfriendly patterns (Hot-spots) in
different designs within the same technology node and across different technology nodes, which eluded design rule
check (DRC), but detected again and again in OPC verification step. Since Model-based OPC tool applies OPC on
whole-chip design basis, individual hot-spot patterns are treated same as the rest of design patterns, regardless of its
severity.
We have developed a methodology to detect those frequently appeared hot-spots in pre-OPC design, as well as post
OPC designs to separate them from the rest of designs, which provide the opportunity to treat them differently in early
OPC flow. The methodology utilizes the combination of rule based and pattern based detection algorithms. Some hotspot
patterns can be detected using rule-based algorithm, which offer the flexibility of detecting similar patterns within
pre-defined ranges. However, not all patterns can be detected (or defined) by rules. Thus, a pattern-based approach is
developed using defect pattern library concept. The GDS/OASIS format hot-spot patterns can be saved into a defect
pattern library. Fast pattern matching algorithm is used to detect hot-spot patterns in a design using the library as a
pattern template database. Even though the pattern matching approach lacks the flexibility to detect patterns' similarity,
but it has the capability to detect any patterns as long as a template exists. The pattern-matching algorithm can be either
exact match or a fuzzy match. The rule based and pattern based hot-spot pattern detection algorithms complement each
other and offer both speed and flexibility in hot spot pattern detection in pre-OPC and post-OPC designs.
In this paper, we will demonstrate the methodology in our OPC flow and the benefits of such methodology application
in production environment for 90nm designs. After the hot spot pattern detection, examples of special treatment to
selected hot spot patterns will be shown.
In this paper, it is described in great details how we perform DOE (Design Of Experiments), simulations, narrowing the
candidates down, and optimizing them to achieve low COO and large process window RET in 65 nm node nested-hole
patterning. We are trying to find best condition of 65 nm tech node nested hole with dry ArF lithography process,
regarding porcess cost redcution and easy access to RETs.
Design For Manufacturing (DFM) has been paid attention as the feature size on chip goes down below the k1 factor of
0.25. Lots of DFM related ideas have been come up, tried, and some of them adopted for wider process window and as a
result, higher yield. As the minimum features are getting shrunk, the design rules become more complicated, but still not
good enough to describe the complexity and limitation of certain patterns that imposes narrow process window, or even
failure of device. Thus, it becomes essential to identify, correct, or remove the litho-unfriendly patterns (more widely
called as hot spots), before OPC. One of the efforts is to write a DFM rules in addition to conventional DRC rules.
In this study, we use the software, called YAM (Yield Analysis Module) to detect hot spots on pre-OPC layouts.
Conventional DRC-based search is not able to surpass YAM, as it enables to identify hot spots in either much easier way
or even ones that are unable to be found by DRC. We have developed a sophisticated methodology to detect and fix
OPC- and/or litho-unfriendly patterns. It is confirmed to enlarge process window and the degree of freedom on OPC
work.
Flare has become a significant problem for low K1 lithography process.[1] It is generally divided into three parts:
long-, local-, short-range. Long-range flare is scattering over a scale of tens of microns, come from reflections within the
projection lens. Short-range is scattering over a scale of about 1 micron or less, come from lens aberrations. And localrange
flare is scattering over about 1 to 10 microns, comes from inhomogenieties within glass and local pattern density.
Especially, local-range flare causes the printed width to vary or degrade printing accuracy. Normally, the local-range
flare effect is increase by local pattern density. Therefore the local flare effect can be reduced if the effect of local pattern
density within die is compensated effectively.
In this paper, we discussed full chip compensation for local flare effect using OPC/DRC method. First of all, we
investigated relationship between local flare and pattern density using test pattern and extracted OPC model according
to pattern density and also analyzed within chip pattern density distribution using DRC. We separated original layout to
OPC target layout according to local pattern density, applied different OPC model to each separated layout. We will
show within chip CD variation was improved after local flare effects reduction.
Flare is unwanted light arriving at the wafer and light causing negative impact on pattern formation. It is caused
by scattered light from lens surfaces, problem on lens design, or problem on lens manufacture. The impact of flare varies
printed line widths or drops CD uniformity accuracy in full chip. And, It is an added incoherent background intensity that
will degrade OPC(Optical Proximity Correction) accuracy[1].
In this paper, we discussed CD variation, MEEF (Mask Error Enhancement Factor) and OPC accuracy by the
flare effects. Flare is bound up with local pattern density. Local pattern density influences background intensity by flare
or stray light. So we studied CD variation, MEEF, OPC modeling data with local pattern density by several experiment.
Also, in this study, we will discuss test pattern drawing for OPC modeling data, analyze CD difference between OPC test
pattern with considering flare effect and test pattern with regardless flare effect and MEEF value by flare effect. MEEF is
main factor that influences lithography process margin. This paper will show test pattern optimization in OPC modeling.
Resolution enhancement technologies (RET), such as optical proximity correction (OPC) help us develop sub-
100nm technology node by using photolithography equipments and materials for 130nm photolithographic process.
Because the resolution of scanner and materials has arrived almost at their limit, small patterns below resolution limit are
more sensitively affected by very small tolerance of various factors which were not considered by major process
parameters such like lens flare, reticle haze, reticle critical dimensional (CD) errors, etc. As patterning small ones under
resolution limit directly means large MEEF (mask error enhancement factor) in photo process, reticle CD errors are
actually magnified on wafer. Therefore, reticle CD errors should be tightly controlled when we try to define small
patterns under resolution limit.
As the feature size shrinks down, the importance of OPC model accuracy grows up for the purpose of ensuring
high pattern fidelity. In conventional process of OPC model generation, we don't concern how mask database CDs are
exactly matched with real reticle CDs, since the specification of reticle CD is enough tight to ignore CD variation on the
reticle such as 1-dimensional CD difference, linearity CD uniformity. But in the process with large MEEF, OPC model
with incorrect CD information of reticle has a bad influence to prediction pattern fidelity.
In this paper, we describe the effect of reticle CD errors on the OPC model accuracy. To quantify that effect, we
compared two cases of OPC model generation. One is making OPC model by using mask database CDs themselves, the
other is by using mask real CDs in 110nm node for poly and metal 1 (damascene) layers. As a consequence of the test,
we can achieve the accuracy OPC model calibrated with reticle CD errors which better predicts wafer CDs and 2-
dimensional images than the model, calibrated by original database CDs.
KEYWORDS: Data modeling, Optical proximity correction, Data conversion, Process modeling, Critical dimension metrology, Reactive ion etching, Scanning electron microscopy, Photomasks, Etching, Image processing
OPC has become an indispensable tool used in deep sub-wavelength lithograph process enabling highly accurate CD
(Critical Dimension) control as design rule shrinks. Rule based OPC was widely acceptable in the past, however it has
recently turned toward model OPC according to the decreasing pattern size. Model based correction was first applied to
the optical proximity phenomenon because the image of sub-wavelength pattern is distorted severely during the optical
image transformation. In addition, more tight CD control required to compensate the process induced error effects from
etch or other process as well optical image can be achieved.
In this paper, we propose advanced OPC method to obtain better accuracy on the final target for sub-90nm technology.
This advanced method converts measured CD data into final CD target by using an equation. We compared the results
from the data converting method, suggested in this paper, with those from post-litho(DI), post-etch (FI) OPC model step
by step. Finally we confirmed that advanced new OPC method gives better accuracy than that from conventional OPC
model
OPC(Optical Proximity Correction) has become an indispensable tool used in deep sub-wavelength lithograph process enabling highly accurate CD (Critical Dimension) control as design rule shrinks. Current model based OPC is a combination of optical and process model to predict lithography process. At this time, the accurate OPC model can be made by accurate empirical measurement data. Therefore empirical measurement data affects OPC model directly. In the case of gate layer, it affects to device performance significantly and CD spec is controlled tightly. Because gate layer is hanging on between active area and sti area, the gate CD is affected by different sub layer stack and step height. This paper will analyze that the effect of sub layer on the OPC model and show difference EPE value results at the patterns such as iso line, iso space,pitch, line end and T_junction between poly and gate model using constant threshold model.
KEYWORDS: Optical proximity correction, Logic, Databases, System on a chip, Data modeling, Photomasks, Instrument modeling, Manufacturing, Electronics, Distortion
It is becoming difficult to achieve stable device functionality and yield due to the continuous reduction of layout dimensions. Lithographers must guarantee pattern fidelity throughout the entire range of nominal process variation and diverse layout.
Even though we use general OPC method using single model and recipe, we usually expect to obtain good OPC results and ensure the process margin between different devices in the sub-100nm technology node.
OPC Model usually predicts the distortion or behavior of layout through the simulation in the range of measured data. If the layout is out of range from the measured data, or CD difference occurred from the topology issue, we can not improve the OPC accuracy with a single OPC model.
In addition, as the design rule has decreased, it is extremely hard to obtain the efficient OPC result only with a single OPC recipe. We can not extract the optimized single OPC recipe which can cover all the various device and layout. Therefore, we can improve the OPC accuracy and reduce the turn around time related to the OPC operation and mask manufacturing in sub-100nm technology node by applying the optimized multi OPC recipes to the device which contains the various patterns like SoC.
KEYWORDS: Photomasks, Semiconducting wafers, Deep ultraviolet, Lithography, Laser systems engineering, Electron beam lithography, Critical dimension metrology, Scanners, Back end of line, Data modeling
The higher productivity of the DUV laser mask lithography system compared to the 50-KeV e-beam system offers the benefit of mask cost down at low k1 lithographic process. But the major disadvantage of the laser mask writing system is rounding effect of contact hole and line end. In this paper, we study wafer process margin effect of corner rounded contact hole and present mask CD specification of corner rounded contact hole written by DUV laser lithography system compared to 50KeV writing tool. The contact hole rounding changes contact hole area at the same mask CD and also change MEEF(Mask Error Enhancement Factor) even though the contact hole area is compensated by adjusting mask bias. If one change EBM3500 mask writer machine to Alta4300 mask writer machine for 160nm contact hole using KrF and 6% HT-PSM, one has to change mask bias, 3.2nm, to meet same wafer process condition.. The MEEF of ALTA4300 mask is 1.6% higher than that of EBM3500 mask at same effective target mask CD. And the mask CD specification written by ALTA4300 has to be set more tightly about 1.3 ~ 1.5% to meet same wafer process margin with EBM3500 mask.
Optical Proximity Correction (OPC) often reaches its limitation, especially low-k imaging. It results in yield drop by bridging, pinching, and other process window sensitive issues. It happens more when the original layout contains OPC-unfriendly patterns. With OPC-unfriendly layout, OPC model generates totally unexpected results such as narrow space, small jog, small serif and etc. Those unexpected OPC results induce bridged patterns as well as narrow process margin. And they will give direct yield loss of device.
Thus, it is critical to implement the flow for Litho Friendly Design (LFD) and nevertheless simulation-based OPC verification. In this study, a new approach of OPC has been tested, which contains the simulation based analysis of OPC failure and in turn out reconstruct OPC features in a way to fix not only bridging and pinching but also to improve process window. This proves to reduce mask respin by 50% or more. It also has been tried to be a complementary checking in addition to conventional CD monitor in pilot production.
Since an OPC engine makes model to fit wafer printed CD of OPC test mask to simulation CD of test pattern layout, the target CD of OPCed mask is not design CD but the CD of OPC test mask. So, the CD difference between OPC test mask and OPCed mask is one of the most important error source of OPC. We experimentally obtained OPC CD error of several patterns such as iso line, iso space, dense line, line end, effected by the mask MTT (mean to target) difference of the two masks on of 90nm logic pattern with an ArF attenuated mask having designed different MTT. The error is compared to simulated data that is calculated with MEEF (mask error enhancement factor) and EL (exposure latitude) data of these patterns. The good agreement of the experimental and calculated OPC error effected mask MTT error can make OPC error are predicted by mask CD error. Using by these calculation, we made mask CD window to meet OPC spec for 90nm ArF process.
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