Ms. Judith Yep Profile

Judith Yep

at KLA Singapore

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Proceedings Article | 20 March 2020 Paper

Machine learning for Tool Induced Shift (TIS) reduction

Shlomit Katz, Boaz Ophir, Udi Shusterman, Anna Golotsvan, Liran Yerushalmi, Efi Megged, Yoav Grauer, Jian Zhang, Alimei Shih, Shi-Ming Wei, Judith Yep, Fiona (Shuk Fan) Leung, Pek Beng Ong

Proceedings Volume 11325, 113252C (2020) https://doi.org/10.1117/12.2550747

KEYWORDS: Semiconducting wafers, Overlay metrology, Machine learning, Metrology, Data modeling, 3D modeling, Performance modeling

Read Abstract +

Tool induced shift (TIS) is a measurement error attributed to tool asymmetry issues and is commonly used to measure the accuracy of metrology tools. Overlay (OVL) measurement inaccuracy is commonly caused by lens aberration, lens alignment, illumination alignment and asymmetries on the measured target. TIS impacts total measurement uncertainty (TMU) and tool-to-tool matching, and TIS variation across wafer can account for inaccuracy, if not fully corrected, as it depends on the incoming process condition. In addition, both lot-to-lot and wafer-to-wafer process variation are influenced by TIS in terms of overlay performance, which also includes metrology tool-to-tool efficiency in terms of throughput. In the past, TIS correction was only done using a small sampling, resulting in additional error in the measurement which was not corrected. Hence, a new methodology is explored to improve overlay measurement accuracy by Modeled-TIS (M-TIS). This paper discusses a new approach of harnessing Machine Learning (ML) algorithms to predict TIS correction on imaging-based overlay (IBO) measurements at the after-develop inspection (ADI) step. KLA’s ML algorithm is trained to detect TIS error contributors to overlay measurements by training a model to find the required TIS correction for one wafer. This information, along with additional accuracy metrics, is then used to predict the TIS for other wafers, without having to actually measure the wafers. In this paper, we present the results of a case study focusing on DRAM and 3D NAND production lots.

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