Lithography becomes much more challenging when CD shrinks to 22nm nodes. Since EUV is not ready, double
patterning combined with Resolution Enhancement Technology (RET) such as shrink techniques seems to be the most
possible solution. Companies such as TSMC[1] and IBM[2] etc. are pushing out EUV to extend immersion ArF
lithography to 32nm/22nm nodes.
Last year, we presented our development work on 32nm node contact (50nm hole at 100nm pitch) using dry ArF
lithography by double patterning with SAFIER shrink process[3]. To continue the work, we further extend our dry litho
capability towards the 22nm node. We demonstrated double patterning capability of 40nm holes at 80nm pitch using
ASML XT1400E scanner. It seems difficult to print pitches below 140nm on dry scanner in single exposure which is
transferred into 70nm pitch with double patterning.
To push the resolution to 22nm node and beyond, we developed ArF immersion process on ASML XT1700i-P system at
the College of Nanoscale Science and Engineering (Albany, NY) combined with a SAFIER process. We achieved single
exposure process capability of 25nm holes at 128nm pitch after shrink. It enables us to print ~25nm holes at pitch of
64nm with double patterning.
Two types of hard mask (HM), i.e. TIN and a-Si were used in both dry and immersion ArF DP processes. The double
patterning process consists of two HM litho-shrink-etch steps. The dense feature is designed into two complementary
parts on two masks such that the density is reduced by half and minimum pitch is increased by at least a factor of 21/2
depending on design. The complete pattern is formed after the two HM litho-shrink-etch steps are finished.
It is challenging to develop 45nm node contact hole using dry ArF lithography process with acceptable lithographic margin due to small process window and large mask error enhancement factor (MEEF). No single process using conventional lithography without resolution enhancement technique (RET) application will meet DOF requirement of 45nm node contact hole. We have developed dry ArF lithography processes for 45nm node contact hole on scanner ASML XT1400E by applying RETs including off-axis illumination, SAFIER (Shrink Assist Film for Enhanced Resolution) process, EFESE (focus scan), etc.
The paper will discuss process window through pitches with optimized illumination, and where to separate pitches in case of double exposure with consideration of DOF and OPC model simulation. It will look into the effect of EFESE on DOF improvement, proximity, and MEEF at various pitches. The paper will also discuss OPC modeling strategy for 45nm node contact/via hole. It will analyze the effect of OPC grid size on OPC run time, file size, and edge placement error (EPE).
To extend process further to 32nm node, we demonstrated the process capability for 32nm node hole using double patterning technique. We achieved 50nm final hole CD with pitch of 100nm. A hard mask (HM) technique was implemented in the process. The dense feature is designed into two complementary parts on two masks such that the density is reduced by half and minimum pitch is increased by at least a factor of 21/2 depending on design. The complete patters are formed with two litho-etch process steps. After the first mask litho process, the HM is etched. Then the second mask litho process is carried out and followed by a second HM etch and main etch.
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