Design tools exploit design hierarchy for speed, efficiency and reuse. Conventional optical proximity correction (OPC) tools process design layouts in a sequential mode layer by layer to ensure stability of the resolution enhancement technology (RET) corrections. A typical sub-100 nm design layout is very large and OPC expands the data volume significantly. The large data volumes and long run-times associated with conventional OPC are becoming critical bottlenecks for manufacturing turn-around time.
In a full-chip layout comprised of a library of cells, a cell may be instantiated thousands of times. Aprio's incremental OPC technology applies a design-like methodology that exploits the hierarchical structure of the layout. OPC is applied once per master cell rather than once per cell placement. The master cells are reused and can be instantiated across different designs. These pre-OPC'ed cells are reconverged or "stitched" together at their interacting halo areas to build up proximity-corrected, hierarchical layouts. This alleviates the need to run OPC sequentially on multiple designs where the master cell is instantiated, thus leading to significantly reduced run-time and data size. We are able to extend this to applications such as manufacturing engineering change order (ECO) handling and design re- spins without the need to rerun the entire OPC layout. Since our incremental technology can "stitch" together previously OPC corrected areas and cells, we are able to combine less complex areas along with "critical-care" areas leading to a more robust final layout that is optimally designed for manufacturing.
Optical proximity corrections (OPC) applied to design layouts are targeted for the nominal process condition FoEo that maintains manufacturing throughput and yield. For designs at 130 nm and above, this is usually sufficient to provide the needed resolution enhancement technology (RET) corrections for high-yield manufacturing. However, for sub-100 nm designs, lack of feature fidelity across the process window becomes a significant contributor to yield loss. It becomes critical to simulate across the lithography process window to predict feature behavior over a wide range of focus and exposure (FE) conditions. KLA-Tencor's DesignScan tool simulates the performance of a design across the process window and detects any defects which are then flagged for repair.
In the conventional OPC flow, correction of defects entails changing the OPC recipe and redecorating the entire layout. Aprio's reconfigurable OPC technology allows one to compute more aggressive OPC corrections at the error locations. This reconfigured OPC replaces the original corrections only at the error locations. This allows prior OPC results to be re-used. The halo or boundary areas associated with the stitching of the modified OPC are simulated and verified and the results are converged back into the layout. This allows the designer to start with a nominal OPC design and by applying reconfigurable OPC technology, eliminate printability errors in the process window, expand the process window, resulting in more robust design performance across the process window. This mask design inspection and optimization method improves yield and shortens cycle time to first wafers, thus providing closure for the design to manufacturing loop.
In order to extend the life of DUV lithography to the 130 nm design rule and below, optical proximity correction (OPC) and phase shift masks (PSM) have become increasingly common. The implementation of low k lithography in IC production requires inspection systems with smaller linewidth capability and higher sensitivity to obtain high yields in advanced reticle production. This paradigm presents greater inspection challenges for current UV tools. When inspections are run on advanced reticles on current tools, the number of false and nuisance defect detections are so high as to make inspecting these reticles unmanageable. The amount of desense required to bring false and nuisance detections down also causes real defects to be missed. The TeraStar SLF27 is the next generation reticle inspection tool from KLA-Tencor. The TeraStar addresses these problems with new algorithms that allow inspection of OPC features without desensing the detectors. Complementing this are triple-beam optics and the ability to run pattern and STARlight inspections concurrently giving a net gain in the throughput and productivity of the tool. Here we present the first results from the use of the TeraStar in a production environment.
In order to extend the life of DUV lithography to the 130 nm design rule and below, optical proximity correction (OPC) and phase shift masks (PSM) have become increasingly common. The implementation of low k1 lithography in IC production requires inspection systems with smaller linewidth capability and higher sensitivity to obtain high yields in advanced reticle production. This paradigm presents greater inspection challenges for current UV tools. When inspections are run on advanced reticles on current tools, the number of false and nuisance defect detections are so high as to make inspecting these reticles unmanageable. The amount of de-sense required to bring false and nuisance detections down also causes real defects to be missed. The TeraStar SLF27 is the next generation reticle inspection tool from KLA-Tencor. The TeraStar addresses these problems with new algorithms that allow inspection of OPC features without desensing the detectors. Complementing this are triple-beam optics and the ability to run pattern and STARlightT inspections concurrently giving a net gain in the throughput and productivity of the tool. Here we present the first results from the use of the TeraStar in a production environment.
The roadmap to develop smaller and smaller critical dimensions on photomasks has predicated the need for new technologies that can facilitate the repair on a scale that to date has proven difficult to achieve by conventional repai tools. RAVE has developed a novel technology that has application for subtractive repair of defects at and belo the 130 nm design rule.
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