This paper compares several designs of spanning tree adders for 16 and 32 bit widths. The carry select part of the
spanning tree is done using ripple carry and carry skip adders (4, 8 and 16 bits) and compared in terms of delay,
complexity and power consumption. The spanning tree design is also compared with that of a conventional carry
lookahead adder. All the designs are done using only 2 input NAND and NOR gates and inverters in 0.18 μm CMOS
technology. The delay and power consumption is determined by use of simulations performed with Synopsys and
Cadence design tools. The spanning tree adder realized with carry skip adders is about 40% faster than the carry
lookahead adder with an approximate increase of 17% in complexity and 22% in power.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.