Transistor architectures below the 7 nm node are significantly enabled by EUV lithography, with single exposure EUV processes simplifying small pitch patterning processes. However, EUV stochastics are a significant hurdle in meeting aggressive process assumption targets and achieving high yields. In particular, line edge roughness and line width roughness (LER and LWR) at EUV patterned gate have been identified as key limiters of device performance and yield within these nodes. Here, we study the impact of different illumination schemes on gate LER and LWR. We specifically utilize NILS to target LER and LWR reduction, with high NILS observed to primarily reduce high frequency roughness. Post etch, a largely illumination independent reduction in the mid and high frequency regimes is observed. Finally, impact of illumination on long channel gate patterning is assessed and a NILS independent LWR response is observed both post development and etch.
Gate all around stacked nanosheet FET’s have emerged as the next technology to FinFET’s for beyond 7-nm scaling. With EUV technology integrated into manufacturing at 7nm, there is great interest to enable EUV direct print patterning for nanosheet patterning as a replacement to complex double patterning schemes. While front-up sheet pitches and gate pitches expected for the beyond 7nm node fall well within the EUV direct print regime (>40nm), it is unclear if direct print solutions can meet variation requirements at technology minimum sheet widths and gate lengths. Here, we explore the crossover point between direct print EUV and optical/EUV based double patterning processes for sheets and gates in the 40 – 50 nm sheet pitch/CPP regime. We demonstrate that to enable the minimum sheet widths of <20nm required for the technology, direct bright field print with shrink results in high variability. We develop a tone invert process with darkfield sheet print that utilizes a polymerizing etch to reduce variability and achieve sub-20nm sheet widths with reduced variability, comparable to a self-aligned double patterning (SADP) process. With gate length variation requirements being tighter, we show that SADP still yields a considerable improvement in line edge/width roughness over a direct print process. We project EUV technology into the future to quantify improvements that would enable direct printed gates that match SADP. Our results will provide a guideline to down-select patterning processes for the nanosheet front end while optimizing cost and complexity.
As device scaling continues, controlling defect densities on the wafer becomes essential for high volume manufacturing (HVM). One type of defect, the non-selective SiGe nodule, becomes more difficult to control during SiGe epitaxy (EPI) growth for p-type field effect transistor (pFET) source and drain. The process window for SiGe EPI growth with low nodule density becomes extremely tight due to the shrinking of contact poly pitch (CPP). Any tiny process shift or incoming structure shift could introduce a high density of nodules, which could affect device performance and yield. The current defect inspection method has a low throughput, so a fast and quantitative characterization technique is preferred for measuring and monitoring this type of defect.
Scatterometry is a fast and non-destructive in-line metrology technique. In this work, novel methods were developed to accurately and comprehensively measure the SiGe nodules with scatterometry information. Top-down critical dimension scanning electron microscopy (CD-SEM) images were collected and analyzed on the same location as scatterometry measurement for calibration. Machine learning (ML) algorithms are used to analyze the correlation between the raw spectra and defect density and area fraction. The analysis showed that the defect density and area fractions can be measured separately by correlating intensity variations. In addition to the defect density and area fraction, we also investigate a novel method – model-based scatterometry hybridized with machine learning capabilities – to quantify the average height of the defects along the sidewall of the gate. Hybridizing the machine learning method with the model-based one could also eliminate the possibility of misinterpreting the defect as some structural parameters. Furthermore, cross-sectional TEM and SEM measurement are used to calibrate the model-based scatterometry results. In this work, the correlation between the SiGe nodule defects and the structural parameters of the device is also studied. The preliminary result shows that there is strong correlation between the defect density and spacer thickness. Correlations between the defect density and the structural parameters provides useful information for process engineers to optimize the EPI growth process. With the advances in the scatterometry-based defect measurement metrology, we demonstrate such fast, quantitative, and comprehensive measurement of SiGe nodule defects can be used to improve the throughput and yield.
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