KEYWORDS: Semiconducting wafers, Metals, Back end of line, Silver, Optical lithography, Transmission electron microscopy, Nanosheets, Front end of line, Wafer bonding, Semiconductors
The saturation in dimensional scaling has clearly impacted the semiconductor technology roadmap. The extension of patterning cliffs through new tools and multi-patterning lithography, as well as the introduction of innovative scaling boosters is helping in optimally scaling the Power-Performance-Area (PPA) metrics. However, because of the increase in the process complexity and reduced area benefits, manufacturing cost is increasing. Therefore, moving to a PPA-Cost (PPAC) methodology to monitor and analyze the cost of a technology is becoming increasingly necessary.
Sequential and monolithic complementary FET (CFET) have become the most attractive device options for continuing the area scaling of SRAM beyond 5-Å-compatible technology (A5). The stacked architecture of CFET has eradicated the need for PMOS and NMOS (PN) separation and thereby enables cell height scaling of 40% compared to 10-Å-compatible technology (A10) forksheet (FS) SRAM. However, the routing becomes challenging with aggressive area scaling. This work proposes interconnect designs for A5 CFET SRAM and explores process integration options for corresponding solutions.
KEYWORDS: Semiconducting wafers, Back end of line, Nanosheets, Logic, Standards development, Metals, Fin field effect transistors, Semiconductors, Optical lithography, Nanotechnology
Fin depopulation, thinner and taller fins, and the step towards Nanosheet technologies has been helping in maintaining the rhythm of the semiconductor technology roadmap. Nevertheless, further area scaling causes a drastic reduction in active width as well as a challenging routability. On this regard, the Complementary-FET is a strong contender as device for next generation technologies. The stack of p- on n-FETs offers several opportunities for device scaling and optimization. However, it also poses several challenges that need to be carefully analyzed in a design-technology cooptimization framework.
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