As the cell size of memory devices continues to shrink, tighter On-Product Overlay (OPO) specifications toward a 1nm OPO budget are required. EUV (extreme ultraviolet lithography) production was adopted in 2019 and the next lithography development known as High NA EUV will fulfill market demand beyond 5nm and 3nm process nodes. High NA EUV requires shrinking the scribe line from 50μm to 40μm, which results in new requirements for the target size to be smaller than the current size μDBO (16x16μm) and AIM (24x24μm) targets. The reduction in the scribe line is certainly beneficial to chipmakers for wafer real estate and yield. For metrology measurements in high-volume manufacturing (HVM), the main optical overlay (OVL) metrology usually uses imaging-based overlay (IBO) technology, while in other cases diffraction-based overlay (DBO) and scatterometry-based overlay (SCOL) are used. All methods (IBO, DBO, and SCOL) face the same challenge of target size reduction. For instance, IBO targets require a restricted number of grating bars. Most importantly, the smaller the target size, the less kernel information affects measurement quality. The spot size of DBO is larger than the target size, so it increases noise sources from the target's surroundings and affects the OVL accuracy. SCOL technology offers several advantages over IBO and DBO when measuring small targets since the spot size in SCOL is smaller and the spot navigation has a higher control mechanism. In this paper, we present a method called parallax to measure a single-cell overlay using pupil information. We will demonstrate three values: First, the target size can be reduced by up to half. Second, the measurement time is improved by saving navigation time from cell to cell. Third, the optical z-value for each point is reported along with OVL measurements. Additionally, the feasibility of single-cell OVL measurement and optical z-value is demonstrated as KPIs for process control.
As DRAM technology continues to evolve, advanced nodes shrink the device dimensions and raise the requirements for on-product overlay control to reduce residual error. Increased process complexity also demands tighter accuracy and robustness in metrology control, which necessitates new and innovative metrology enhancements and methods. Scatterometry-based overlay (SCOL®) metrology is a unique overlay metrology architecture that uses angle-resolved pupil imaging for overlay analysis and calculation. KLA’s SCOL metrology system offers wide-spectrum tunable laser and multi-wavelength (MWL) illumination patterns along with custom-designed advanced algorithms that provide multiple measurement conditions to meet unique layer and target requirements. This paper demonstrates improved overlay metrology accuracy and residual error on DRAM FEOL critical layer with SCOL technology. Multiwavelength and rotated quadrupole (RQ) illumination in the metrology tool are utilized to provide significantly improved residuals compared with the traditional single-wavelength (SWL) and on-axis illumination.
KEYWORDS: Overlay metrology, Semiconducting wafers, Advanced process control, Scanners, Scatterometry, Process control, Signal processing, Metrology, Control systems, Optical parametric oscillators
As the cell size of memory devices continues to shrink, tighter on-product overlay (OPO) specs require more accurate and robust overlay control. The overlay error budget mainly consists of the reticle, scanner, process, and metrology errors. The metrology budget is generally required to be <10% of the OPO control budget so that the accuracy and robustness of overlay metrology become more crucial as pattern size gets smaller on current 1x nm DRAM nodes. For overlay control in high-volume manufacturing (HVM), the primary optical overlay metrology typically used is Image-Based Overlay (IBO). In many cases, scatterometry overlay (SCOL), using a direct grating-scanning method, was shown to achieve more accurate After Development Inspection (ADI) overlay measurements. Using a tunable source and customized illumination pupil to directly scan within the grating cell, this technology improves accuracy by reducing the contribution of pattern surroundings in the scribe line, resulting in improved OPO control stability. Since the purpose of overlay control is to minimize actual device pattern misregistration, as measured after the etching process (AEI), achieving accurate and stable characterization of the systematic deviation between ADI and AEI overlay known as Non-Zero-Offset (NZO) is critically important. Accurate NZO applied to the scanner via the Advanced-Process-Control (APC) loop enables effective scanner overlay control at the post-lithography ADI step. This paper demonstrates a new scatterometry overlay technology adopted in DRAM use cases that resulted in OPO and NZO stability improvement. In addition, we demonstrate an efficient method to monitor HVM run-to-run overlay performance and NZO stability by comprehensive dataset modeling combining ADI and AEI.
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