Mr. Xu Xu Profile

Xu Xu

PhD Student at Univ of California San Diego

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Author

Publications (10)

Proceedings Article | 19 September 2016 Paper

LAST: Laser Array Space Telescope

Jonathan Madajian, Alexander Cohen, Rebecca Hwang, Chase Bishman, Rachel Reyes, Miguel Bautista, Ryan Tsukamoto, Brandon Pon, Dylan Vanmali, Xu Xu, Nicholas Rommelfanger, Ian Ho, Lucas Lin, Michael Prazak, Patrick Ruehl, Travis Brashears, Nic Rupert, Philip Lubin

Proceedings Volume 9981, 99810B (2016) https://doi.org/10.1117/12.2238453

KEYWORDS: Phased arrays, Space telescopes, Telescopes, Space operations, James Webb Space Telescope, Asteroids, Phase shifts, Computer aided design, Phased array optics, Optical instrument design

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Proceedings Article | 17 October 2008 Paper

Revisiting the layout decomposition problem for double patterning lithography

Andrew Kahng, Chul-Hong Park, Xu Xu, Hailong Yao

Proceedings Volume 7122, 71220N (2008) https://doi.org/10.1117/12.801992

KEYWORDS: Double patterning technology, Photomasks, Lithography, Overlay metrology, Cerium, Feature extraction, Optical lithography, Computer programming, Etching, Manufacturing

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Proceedings Article | 20 October 2006 Paper

A procedure and program to calculate shuttle mask advantage

A. Balasinski, J. Cetin, A. Kahng, X. Xu

Proceedings Volume 6349, 63492B (2006) https://doi.org/10.1117/12.686009

KEYWORDS: Photomasks, Reticles, Databases, Manufacturing, Visualization, Resolution enhancement technologies, Design for manufacturability, Product engineering, Algorithm development, Semiconducting wafers

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A well-known recipe for reducing mask cost component in product development is to place non-redundant elements of layout databases related to multiple products on one reticle plate [1,2]. Such reticles are known as multi-product, multi-layer, or, in general, multi-IP masks. The composition of the mask set should minimize not only the layout placement cost, but also the cost of the manufacturing process, design flow setup, and product design and introduction to market. An important factor is the quality check which should be expeditious and enable thorough visual verification to avoid costly modifications once the data is transferred to the mask shop. In this work, in order to enable the layer placement and quality check procedure, we proposed an algorithm where mask layers are first lined up according to the price and field tone [3]. Then, depending on the product die size, expected fab throughput, and scribeline requirements, the subsequent product layers are placed on the masks with different grades. The actual reduction of this concept to practice allowed us to understand the tradeoffs between the automation of layer placement and setup related constraints. For example, the limited options of the numbers of layer per plate dictated by the die size and other design feedback, made us consider layer pairing based not only on the final price of the mask set, but also on the cost of mask design and fab-friendliness. We showed that it may be advantageous to introduce manual layer pairing to ensure that, e.g., all interconnect layers would be placed on the same plate, allowing for easy and simultaneous design fixes. Another enhancement was to allow some flexibility in mixing and matching of the layers such that non-critical ones requiring low mask grade would be placed in a less restrictive way, to reduce the count of orphan layers. In summary, we created a program to automatically propose and visualize shuttle mask architecture for design verification, with enhancements to due to the actual application of the code.

Proceedings Article | 20 October 2006 Paper

Fast dual graph-based hotspot detection

Andrew Kahng, Chul-Hong Park, Xu Xu

Proceedings Volume 6349, 63490H (2006) https://doi.org/10.1117/12.692949

KEYWORDS: Critical dimension metrology, Lithography, Optical proximity correction, Edge detection, Optical lithography, Detection and tracking algorithms, Process modeling, Metals, Model-based design, Resolution enhancement technologies

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As advanced technologies in wafer manufacturing push patterning processes toward lower-k₁ subwavelength printing, lithography for mass production potentially suffers from decreased patterning fidelity. This results in generation of many hotspots, which are actual device patterns with relatively large CD and image errors with respect to on-wafer targets. Hotspots can be formed under a variety of conditions such as the original design being unfriendly to the RET that is applied, unanticipated pattern combinations in rule-based OPC, or inaccuracies in model-based OPC. When these hotspots fall on locations that are critical to the electrical performance of a device, device performance and parametric yield can be significantly degraded. Previous rule-based hotspot detection methods suffer from long runtimes for complicated patterns. Also, the model generation process that captures process variation within simulation-based approaches brings significant overheads in terms of validation, measurement and parameter calibration. In this paper, we first describe a novel detection algorithm for hotspots induced by lithographic uncertainty. Our goal is to rapidly detect all lithographic hotspots without significant accuracy degradation. In other words, we propose a filtering method: as long as there are no "false negatives", i.e., we successfully have a superset of actual hotspots, then our method can dramatically reduce the layout area for golden hotspot analysis. The first step of our hotspot detection algorithm is to build a layout graph which reflects pattern-related CD variation. Given a layout L, the layout graph G = (V, E_c union E_p) consists of nodes V, corner edges E_c and proximity edges E_p. A face in the layout graph includes several close features and the edges between them. Edge weight can be calculated from a traditional 2-D model or a lookup table. We then apply a three-level hotspot detection: (1) edge-level detection finds the hotspot caused by two close features or "L-shaped" features; (2) face-level detection finds the pattern-related hotspots which span several close features; and (3) merged-face-level detection finds hotspots with more complex patterns. To find the merged faces which capture the pattern-related hotspots, we propose to convert the layout into a planar graph G. We then construct its dual graph G^D and sort the dual nodes according to their weights. We merge the sorted dual nodes (i.e., the faces in G) that share a given feature, in sequence. We have tested our flow on several industry testcases. The experimental results show that our method is promising: for a 90nm metal layer with 17 hotspots detected by commercial optical rule check (ORC) tools, our method can detect all of them while the overall runtime improvement is more than 287X.

Proceedings Article | 20 October 2006 Paper

A general framework for multi-flow multi-layer multi-project reticles design

Andrew Kahng, Xu Xu

Proceedings Volume 6349, 63494A (2006) https://doi.org/10.1117/12.686324

KEYWORDS: Reticles, Photomasks, Semiconducting wafers, Dysprosium, Manufacturing, Chemical mechanical planarization, Optical alignment, Algorithms, Wafer dicing, Prototyping

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The aggressive scaling of VLSI feature size and the pervasive use of advanced reticle enhancement technologies leads to dramatic increases in mask costs, pushing prototype and low volume production designs at the limit of economic feasibility. Multiple project wafers (MPW), or "shuttle" runs, provide an attractive solution for such designs, by providing a mechanism to share the cost of mask tooling among up to tens of designs of the same technology flow. However, delay cost associated with schedule alignment is ignored in previous work. The saving on mask cost may be easily surpassed by the profit loss due to the schedule alignment. Therefore, Multi- flow Multi-layer Multi-project Reticles (MFMLMPR) become a more viable mask-cost saving technique for low volume production since it share the mask cost between different layers of the same design and between designs of different technology flows. However, MFMLMPR design introduce complexities not encountered in traditional single-flow or single-layer reticles. In this paper we propose the first design flow for MFMLMPR aimed at minimizing the total manufacturing cost (including mask cost, wafer cost and delay cost) to fulfill given die production volumes. Our flow includes three main steps: (1) schedule-aware project partitioning with multi-flow embedding (2) multi-frame reticle design, and (3) multi-project frame floorplanning. Our contributions are as follows. For the first step, a fast iterative matching algorithm is proposed to calculate the mask cost for multi-flow embedding with consideration of all practical manufacturing costs. We then propose an integer linear programming (ILP) based method for optimal manufacturing cost minimization. Since ILP suffers from impractically long runtimes when the number of projects is large, we propose a sliding time window heuristic to exhaustively search the solution space for the best tradeoff between mask cost and delay cost. For the second step, we propose an ASAP frame embedding heuristic to minimize the mask cost. Finally, a "generalized chessboard" floorplan with simulated annealing is proposed to generate more dicing friendly frame floorplans for multi-flow projects, observing given maximum reticle sizes. We have tested our flow on production industry testcases. The experimental results show that our schedule-aware project partitioner yields an average reduction of 58.4% in manufacturing cost. The reduction of mask cost is around 46.3% compared with use of traditional layer-by layer checking methods. Our generalized chessboard floorplanner leads to an average reduction of 22.8% in the required number of wafers compared to the previous best reticle floorplanner.

Proceedings Article | 27 June 2006 Paper

Multi-project reticle design and wafer dicing under uncertain demand

Andrew Kahng, Ion Măndoiu, Xu Xu, Alexander Zelikovsky

Proceedings Volume 6281, 628104 (2006) https://doi.org/10.1117/12.692627

KEYWORDS: Semiconducting wafers, Reticles, Wafer dicing, Photomasks, Manufacturing, Algorithms, Chemical mechanical planarization, Prototyping, Detection and tracking algorithms, Statistical analysis

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Proceedings Article | 20 May 2006 Paper

Fast yield-driven fracture for variable shaped beam mask writing

Andrew Kahng, Xu Xu, Alex Zelikovsky

Proceedings Volume 6283, 62832R (2006) https://doi.org/10.1117/12.681805

KEYWORDS: Photomasks, Vestigial sideband modulation, Manufacturing, Resolution enhancement technologies, Computer programming, Image segmentation, Beam shaping, Semiconducting wafers, Computed tomography, Reticles

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Increasing transistor densities, smaller feature sizes, and the aggressive use of RET techniques with each successive process generation have collectively presented new challenges for current fracture tools, which are at the heart of layout data preparation. One main challenge is to reduce the number of small dimension trapezoids (slivers) to improve mask yield since the sliver count reflects the risk of mask critical-dimension errors. Some commercial tools are available for handling the sliver minimization problem in fracture, such as CATS from Synopsys and Fracturem from Mentor Graphics. However, the number of slivers in the existing fracture solutions can be significantly reduced. The integer linear programming (ILP) method has been previously applied to find the optimal fracture but has not explored potential benefits from additional ray-segments. Unfortunately, the ILP becomes prohibitively slow for polygons with the large number of vertices and heuristic partitioning of large polygons may severely degrade the solution quality. In this paper, we propose a new ray-segment selection heuristic which can find a near-optimal fracture solution in practical time while being flexible enough to take into account all specified requirements. We fist divide the rectilinear region with all rays from the concave points and formulate the fracture problem as a sequential ray-segment selection problem. Each ray segment is assigned a weight based on its probability to form a sliver. All ray segments to be selected are placed in a candidate pool. An iterative "gain" based process is used for fast and efficient selecting ray segments from the candidate pool and dynamic update of ray segments and their gains. Further reduction of the number of slivers is achieved by auxiliary ray-segments. The resulted runtime overhead is reduced by a rule-based auxiliary ray-segments addition method which achieves a tradeoff between the sliver number reduction and runtime overhead. Compared with state-of-art sliver-driven fracturing tools, the proposed method reduces the number of slivers in the fractures of two industry testcases by 76.7% and 58.6%, respectively, without inflating the runtime and shot count. Similarly, compared with the previous ILP based fracture methods, the new method reduces the number of slivers by 56.1% and 2.2%, respectively, with more than 60X speedup and insignificant shot count overhead. The reduction in the sliver number is primarily due to the introduction of additional ray-segments. The proposed method can also solve the reverse-tone fracture problem in practical time for large industry testcases.

Proceedings Article | 9 November 2005 Paper

Yield-driven multi-project reticle design and wafer dicing

Andrew Kahng, Ion Mandoiu, Xu Xu, Alex Zelikovsky

Proceedings Volume 5992, 599249 (2005) https://doi.org/10.1117/12.632036

KEYWORDS: Semiconducting wafers, Reticles, Wafer dicing, Photomasks, Chemical mechanical planarization, Optimization (mathematics), Prototyping, Optical alignment, Computer programming, C++

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Proceedings Article | 28 June 2005 Paper

Wafer topography-aware optical proximity correction for better DOF margin and CD control

Puneet Gupta, Andrew Kahng, Chul-Hong Park, Kambiz Samadi, Xu Xu

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.620379

KEYWORDS: Optical proximity correction, Laser sintering, Metals, Critical dimension metrology, Chemical mechanical planarization, Semiconducting wafers, Lithography, Tolerancing, SRAF, Standards development

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Proceedings Article | 6 December 2004 Paper

Yield- and cost-driven fracturing for variable shaped-beam mask writing

Andrew Kahng, Xu Xu, Alex Zelikovsky

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.568526

KEYWORDS: Photomasks, Vestigial sideband modulation, Manufacturing, Computer programming, Resolution enhancement technologies, Beam shaping, Semiconducting wafers, Reticles, Raster graphics, Heart

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