Wire transfer of charge packets for on-chip CCD signal processing

Eric R. Fossum

doi:10.1117/12.19451

1 July 1990 Wire transfer of charge packets for on-chip CCD signal processing

Eric R. Fossum

Proceedings Volume 1242, Charge-Coupled Devices and Solid State Optical Sensors; (1990) https://doi.org/10.1117/12.19451
Event: Electronic Imaging: Advanced Devices and Systems, 1990, Santa Clara, CA, United States

Abstract

A structure for the virtual transfer of charge packets across metal wires is described theoretically and is experimentally verified. The structure is a hybrid of charge-coupled device (CCD) and bucket-brigade device (BBD) elements and permits the topological crossing of charge-domain signals in low power signal processing circuits. A test vehicle consisting of 8-, 32- and 96-stage delay lines of various geometries implemented in a double-poly, double-metal foundry process was used to characterize the wire-transfer operation. Transfer efficiency ranging between 0.998 and 0.999 was obtained for surface n-channel devices with clock cycle times in the range from 40 nsec to 0.3 msec. Transfer efficiency as high as 0.9999 was obtained for buried n-channel devices. Good agreement is found between experiment and simulation.

Citation Download Citation

Eric R. Fossum "Wire transfer of charge packets for on-chip CCD signal processing", Proc. SPIE 1242, Charge-Coupled Devices and Solid State Optical Sensors, (1 July 1990); https://doi.org/10.1117/12.19451

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