As the semiconductor industry continues to push the limits of integrated circuit fabrication, reliance on extreme ultraviolet lithography (EUVL) has increased. Additionally, it has become clear that new techniques and methods are needed to mitigate pattern defectivity and roughness at lithography and etch process and eliminate film-related defects. These approaches require improvements to the process chemicals and the lithography process equipment to achieve finer patterns. ESPERTTM (Enhanced Sensitivity develoPER TechnologyTM) technique has been developed and optimized to fulfil this novel development need. ESPERTTM has demonstrated a capability that can enhance the developing contrast between the EUV exposed and unexposed areas. This paper reviews 23 nm pitch line and space and sub-40 nm pitch pillars which were realized by optimized illuminators with 0.33 NA single exposure, and we will show how ESPERTTM helped improve the minimum critical dimension size, defectivity, roughness and electrical yield at the finer patterns.
One of the key steps in the pattern formation chain of extreme ultraviolet (EUV) lithography is the development process to resolve the resist pattern after EUV exposure. The traditional development process might be insufficient to achieve the requirements of ultra-high-resolution features with low defect levels. The aim of this paper is to establish a process to achieve a good roughness, a low defectivity at a low EUV dose, and capability for extremely-high-resolution for high numerical aperture (NA) and hyper-NA EUV lithography. A new development method named ESPERT™ (Enhanced Sensitivity develoPER Technology™) has been introduced to improve the performance of metal oxide-resists (MOR). ESPERT™ as a chemical super resolution technique effectively apodized the MOR chemical image, improving chemical gradient (higher exposure latitude (EL)) and reducing scums (fewer bridge defects). This new development method can also keep the resist profile vertical to mitigate the break defects. The performances of the conventional development and ESPERT™ were evaluated and compared using 0.33 NA EUV, 0.5 NA EUV, and electron beam (EB) exposures, for all line-space (LS), contact hole (CH), and pillar (PL) patterns. Using 0.33 NA EUV scanners on LS patterns, both bridge and break defects were confirmed to be reduced for all 32-nm-pitch, 28-nm-pitch, 26-nm-pitch LS patterns while reducing the EUV dose to size (DtS). In the electrical yield (1 meter length) test of breaks/bridges of 26-nm pitch structures, ESPERT™ reduced EUV dose while its combo yield was almost 100% over a wide dose range of 20mJ/cm². For CH patterns, in the case of 32-nm-pitch AEI (after etch inspection), EL was increased 7.5% up to 22.5%, while failure free latitude (FFL) was widened from 1-nm to 4-nm. A 16-nm-pitch LS pattern was successfully printed with 0.5 NA tool, while a 16-nm-pitch PL and an 18-nm-pitch CH patterns were also achieved with an EB lithography by ESPERT™. With ESPERT™, there was no pillar collapse observed for 12-nm half-pitch PL by 0.5 NA and 8-nm half-pitch PL by EB. With all the advantages of having a high exposure sensitivity, a low defectivity, and an extremely-high-resolution capability, this advanced development method is expected be a solution for high-NA EUV towards hyper-NA EUV lithography.
As the semiconductor industry continues to push the limits of integrated circuit fabrication, reliance on extreme ultraviolet lithography (EUVL) has increased. Additionally, it has become clear that new techniques and methods are needed to mitigate pattern defectivity and roughness after lithography and etch processes and eliminate film-related defects. These approaches require further improvements to the process chemicals and the lithography process equipment to achieve finer patterns. The ESPERTTM (Enhanced Sensitivity develoPER TechnologyTM) technique has been developed and optimized to fulfil this novel development need. The ESPERTTM has demonstrated a capability that can enhance the developing contrast between the EUV exposed and unexposed areas. This paper reviews that 23 nm pitch line and space and sub-40 nm pitch pillars patterns were realized by high NILS illuminations with 0.33 NA single exposure, and we will show the ESPERTTM helped reduce the minimum critical dimension size, defectivity and roughness at the finer patterns.
One of the key steps in the pattern formation chain of extreme ultraviolet (EUV) lithography is the development process to resolve the resist pattern after EUV exposure. A simple traditional development process might be insufficient to clear the holes in contact-hole (CH) patterns and often causes missing hole defects around target-CD. In prior papers, a new development method named ESPERT™ (Enhanced Sensitivity develoPER Technology™) has been introduced to improve the performance of metal oxide-resists (MOR) for line/space (L/S) and pillar patterns. ESPERT™ as a chemical super resolution technique effectively apodized the MOR chemical image, improving chemical gradient and reducing scums. In this work, this development technique was optimised for CH patterns to reduce both the local CD uniformity (LCDU) and to reduce the levels of missing contact holes at a lower exposure dose. This is made possible thanks to the capability of the updated version of ESPERT™ that can effectively remove the scums (resist residues) inside CH to extend the missing hole defect margins. The high development contrast of the new development technique results also in a much higher exposure latitude. Using 0.33 NA EUV scanners on 36-nmpitch hexagonal patterns, the new development enhanced exposure latitude (EL), failure free latitude (FFL), and failure free dose ranges at both ADI (after development inspection) and AEI (after etch inspection) for two diverse types of MORs. For instance, in the case of the reference MOR developed by ESPERT™, CHs were nicely transferred to a TiN layer, even for small CD holes of 14.7 nm. If compared to the data by conventional development, using the new method, the EL was increased from 16.0% to 49.1%, the FFL was extended from 2 nm to 6 nm, and the failure free dose range was increased from 13.3% to 72.2%. It was also possible to have EUV dose-to-size (DtS) of 28 mJ/cm² with EL of 49.9% at ADI, using the new development. With all those advantages, this new development method is expected to be the solution for CH pattern formation of negative tone MORs in EUV lithography.
Extreme ultraviolet lithography (EUVL) has overcome significant challenges to become an essential enabler to the logic and memory scaling roadmap. Despite its significant progress, resist photo speed, and defectivity remains the main concerns for high-volume manufacturing. To overcome these issues, high-performance EUV resist processes are needed. The high-performance resist process must simultaneously meet multiple requirements, such as a high resolution, high sensitivity, low roughness, low defect level, and good global CD uniformity (CDU). One of the high-performance resist candidates for future EUV scaling, and high NA EUV is Metal Oxide Resist (MOR). In our work, we introduce the new coater/developer hardware and new resist development techniques to improve photo speed, defectivity, and CDU without degradation of roughness in MOR. We will show that the new development methods significantly improve EUV dose to size (DtS) and micro-bridge (MB) while maintaining resist roughness performance post litho and post-etch. The new coater/developer hardware and processes are evaluated through a robust characterization methodology that includes an understanding of the defect modes at ADI (after development inspection) and AEI (after etch inspection), as well its ultimate correlation to electrical yield.
As the limits of EUV single exposure direct printing are being explored there is a need for etch processes that can transfer small features and reduce defectivity. The implementation of high numerical aperture (NA) EUV scanner tool will allow for printing of sub-10 nm features in a single exposure. However, it reduces the depth of focus, thus requires thinner photoresist coatings. In preparation for high NA (0.55) we explore the etch implications of thin EUV photoresists. Here we show two different strategies for bridge defect reduction during etch and break elimination with selective deposition during the etch process.
In this study we examine several innovations. In lithography, we introduce our latest progress on metal oxide resist (MOR) to extend defectivity window, improve photo-speed, and wafer uniformity control by leveraging new resist development techniques.
On the plasma etch front, we focus on plasma-resist interactions and the impact of the pattern transfer process. Gas chemistry and plasma characteristics can modulate resist rectification, leading to a widening of the defectivity window and smoothing of pattern roughness. Especially, when reducing line-space pattern defectivity, correlations between plasma characteristics and microbridge defect numbers point to a proper process regime for patterning in the sub 30nm pitch era.
EUV (extreme ultraviolet) lithography has been introduced in high volume manufacturing in 2019 and continuous improvements have allowed to push the lithographic performance to the limits of 0.33 NA single exposure. However, stochastic failures, pattern roughness and local critical dimension uniformity (LCDU) are still major challenges that need to be addressed to maintain node shrinkage and improve yield. Together with pitch downscaling, photoresist thickness is decreasing to prevent pattern collapse. A lower depth of focus is also expected with high NA EUV which might even thin further down the resist layer. Being able to transfer the patterns with good fidelity is therefore getting very challenging because the resist “etch budget” is becoming too small to prevent pattern break during plasma etch transfer. A co-optimization of lithography processes, underlayers coating and etch processes is essential to further support the EUV patterning extension.
In this report, recently developed hardware and process solutions to stretch the limits of EUV patterning will be presented. The latest performance for both chemically amplified resists (CAR) and metal oxide resists (MOR) will be introduced, with a focus on defect mitigation, dose reduction strategies and CD stability.
As the semiconductor industry continues to push the limits of integrated circuit fabrication, reliance on extreme ultraviolet lithography (EUVL) has increased. New techniques and methods are needed to mitigate pattern defectivity and roughness using both lithography and etch processes to eliminate film-related defects. These approaches require further improvements to the process chemicals and the lithography process equipment to achieve finer patterns. Additionally, underlayers and resist optimization play a significant role in resist pattern fidelity. This paper reviews the ongoing progress in coater/developer processes that are required to enable EUV patterning by using chemically amplified and metal oxide resists. We will discuss several new techniques for pattern defectivity, roughness, and EUV dose- to- size reduction using coater/developer processes. In addition, we will review our study with various underlayers to enable smaller minimum critical dimension size.
In this talk we present core technology solutions for EUV Patterning and co-optimization between EUV resist and underlayer coating, development and plasma etch transfer to achieve best in class patterning performance. We will introduce new hardware and process innovations to address EUV stochastic issues, and present strategies that can extend into High NA EUV patterning. A strong focus will be placed on dose reduction opportunities, thin resist enablement and resist pattern collapse mitigation technologies. CAR and MOR performance for leading edge design rules will be showcased. As the first High NA EUV scanner is scheduled to be operational in 2023 in the joint high NA lab in Veldhoven, Tokyo Electron will collaborate closely with imec, ASML and our materials partners to accelerate High NA learning and support EUV roadmap extension.
As the industry continues to push the limits of integrated circuit fabrication, reliance on EUV lithography has increased. Additionally, it has become clear that new techniques and methods are needed to mitigate pattern defectivity and roughness at Litho and Etch together with eliminating film-related defects.
These approaches require further improvements to the process chemicals and the lithography process equipment to achieve finer patterns.
In particular improvements in the coater/developer hardware and process are required to enable the use of a wide variety of chemicals as well as compatibility with existing systems.
This paper reviews the ongoing progress in coater/developer processes that are required to enable EUV patterning sub-30nm line and space by using MOR (Metal Oxide Resist).
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