Dr. Dario Gil Profile

Dr. Dario Gil

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Publications (9)

Proceedings Article | 14 March 2019 Open Access

The Future is Quantum

Dario Gil

Proceedings Volume 10957, 1095702 (2019) https://doi.org/10.1117/12.2523971

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Proceedings Article | 16 March 2009 Paper

A computational technique to optimally design in-situ diffractive elements: applications to projection lithography at the resist resolution limit

Gonzalo Feijóo, Jaione Tirapu-Azpiroz, Alan Rosenbluth, Assad Oberai, Jayanth Jagalur Mohan, Kehan Tian, David Melville, Dario Gil, Kafai Lai

Proceedings Volume 7274, 72741E (2009) https://doi.org/10.1117/12.814251

KEYWORDS: Wavefronts, Holograms, Electromagnetism, Near field, Lithography, Optical design, Photomasks, Diffraction gratings, Optical lithography, Spatial frequencies

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Near-field interference lithography is a promising variant of multiple patterning in semiconductor device fabrication that can potentially extend lithographic resolution beyond the current materials-based restrictions on the Rayleigh resolution of projection systems. With H₂O as the immersion medium, non-evanescent propagation and optical design margins limit achievable pitch to approximately 0.53λ/nH₂O = 0.37λ. Non-evanescent images are constrained only by the comparatively large resist indices (typically1.7) to a pitch resolution of 0.5/nresist (typically 0.29). Near-field patterning can potentially exploit evanescent waves and thus achieve higher spatial resolutions. Customized near-field images can be achieved through the modulation of an incoming wavefront by what is essentially an in-situ hologram that has been formed in an upper layer during an initial patterned exposure. Contrast Enhancement Layer (CEL) techniques and Talbot near-field interferometry can be considered special cases of this approach. Since the technique relies on near-field interference effects to produce the required pattern on the resist, the shape of the grating and the design of the film stack play a significant role on the outcome. As a result, it is necessary to resort to full diffraction computations to properly simulate and optimize this process. The next logical advance for this technology is to systematically design the hologram and the incident wavefront which is generated from a reduction mask. This task is naturally posed as an optimization problem, where the goal is to find the set of geometric and incident wavefront parameters that yields the closest fit to a desired pattern in the resist. As the pattern becomes more complex, the number of design parameters grows, and the computational problem becomes intractable (particularly in three-dimensions) without the use of advanced numerical techniques. To treat this problem effectively, specialized numerical methods have been developed. First, gradient-based optimization techniques are used to accelerate convergence to an optimal design. To compute derivatives of the parameters, an adjoint-based method was developed. Using the adjoint technique, only two electromagnetic problems need to be solved per iteration to evaluate the cost function and all the components of the gradient vector, independent of the number of parameters in the design.

Proceedings Article | 16 March 2009 Paper

Benefits and trade-offs of global source optimization in optical lithography

Kehan Tian, Azalia Krasnoperova, David Melville, Alan Rosenbluth, Dario Gil, Jaione Tirapu-Azpiroz, Kafai Lai, Saeed Bagheri, Chia-chen Chen, Bradley Morgenfeld

Proceedings Volume 7274, 72740C (2009) https://doi.org/10.1117/12.814305

KEYWORDS: Diffraction, Printing, Source mask optimization, Optical lithography, Resolution enhancement technologies, Photomasks, Semiconducting wafers, Lithographic illumination, Lithography, Manufacturing

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Proceedings Article | 1 April 2008 Paper

32 nm logic patterning options with immersion lithography

K. Lai, S. Burns, S. Halle, L. Zhuang, M. Colburn, S. Allen, C. Babcock, Z. Baum, M. Burkhardt, V. Dai, D. Dunn, E. Geiss, H. Haffner, G. Han, P. Lawson, S. Mansfield, J. Meiring, B. Morgenfeld, C. Tabery, Y. Zou, C. Sarma, L. Tsou, W. Yan, H. Zhuang, D. Gil, D. Medeiros

Proceedings Volume 6924, 69243C (2008) https://doi.org/10.1117/12.784107

KEYWORDS: Photomasks, Double patterning technology, Logic, Lithography, Etching, Optical lithography, Optical proximity correction, Immersion lithography, Printing, Image processing

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The semiconductor industry faces a lithographic scaling limit as the industry completes the transition to 1.35 NA immersion lithography. Both high-index immersion lithography and EUV lithography are facing technical challenges and commercial timing issues. Consequently, the industry has focused on enabling double patterning technology (DPT) as a means to circumvent the limitations of Rayleigh scaling. Here, the IBM development alliance demonstrate a series of double patterning solutions that enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through innovative processes. These techniques have been successfully employed for early 32nm node development using 45nm generation tooling. Four different double patterning techniques were implemented. The first process illustrates local RET optimization through the use of a split reticle design. In this approach, a layout is decomposed into a series of regions with similar imaging properties and the illumination conditions for each are independently optimized. These regions are then printed separately into the same resist film in a multiple exposure process. The result is a singly developed pattern that could not be printed with a single illumination-mask combination. The second approach addresses 2D imaging with particular focus on both line-end dimension and linewidth control [1]. A double exposure-double etch (DE2) approach is used in conjunction with a pitch-filling sacrificial feature strategy. The third double exposure process, optimized for via patterns also utilizes DE2. In this method, a design is split between two separate masks such that the minimum pitch between any two vias is larger than the minimum metal pitch. This allows for final structures with vias at pitches beyond the capability of a single exposure. In the fourth method,, dark field double dipole lithography (DDL) has been successfully applied to BEOL metal structures and has been shown to be overlay tolerant [6]. Collectively, the double patterning solutions developed for early learning activities at 32nm can be extended to 22nm applications.

Proceedings Article | 29 March 2006 Paper

The effect of photoresist/topcoat properties on defect formation in immersion lithography

G. Wallraff, C. Larson, G. Breyta, L. Sundberg, D. Miller, D. Gil, K. Petrillo, W. Pierson

Proceedings Volume 6153, 61531M (2006) https://doi.org/10.1117/12.657179

KEYWORDS: Semiconducting wafers, Immersion lithography, Particles, Silicon, Rhodamine, Photoresist materials, Digital watermarking, Video, Image processing, Solids

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Proceedings Article | 22 March 2006 Open Access

A year in the life of immersion lithography at Albany Nanotech

Michael Tittnich, John Hartley, Greg Denbeaux, Uzo Okoroanyanwu, Harry Levinson, Karen Petrillo, Chris Robinson, Dario Gil, Dan Corliss, David Back, Stefan Brandl, Christian Schwarz, Frank Goodwin, Yayi Wei, Brian Martinick, Richard Housley, Peter Benson, Kevin Cummings

Proceedings Volume 6151, 615101 (2006) https://doi.org/10.1117/12.663785

KEYWORDS: Nanotechnology, Immersion lithography, Water, Lithography, Semiconductors, Semiconducting wafers, Photoresist developing, Thin film coatings, Scanners, Photoresist materials

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Proceedings Article | 9 March 2006 Paper

Characterization of imaging performance for immersion lithography at NA=0.93

Dario Gil, Jaione Tirapu-Azpiroz, Ryan Deschner, Timothy Brunner, Carlos Fonseca, Jennifer Fullam, Dan Corliss, K. Auschnitt, Peter Vanoppen

Proceedings Volume 6154, 615405 (2006) https://doi.org/10.1117/12.656545

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Immersion lithography, Monte Carlo methods, Scanners, Photomasks, Optical proximity correction, Optical lithography, Lithography, Manufacturing

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Proceedings Article | 12 May 2005 Paper

First microprocessors with immersion lithography

D. Gil, T. Bailey, D. Corliss, M. Brodsky, P. Lawson, M. Rutten, Z. Chen, N. Lustig, T. Nigussie, K. Petrillo, C. Robinson

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.598855

KEYWORDS: Semiconducting wafers, Immersion lithography, Scanners, Lithography, Critical dimension metrology, Semiconductor manufacturing, Manufacturing, Bacteria, Resistance, Polishing

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Proceedings Article | 4 May 2005 Paper

Progress toward developing high performance immersion compatible materials and processes

Karen Petrillo, Kaushal Patel, Rex Chen, Wenjie Li, Ranee Kwong, Peggy Lawson, Rao Varanasi, Chris Robinson, Steven Holmes, Dario Gil, Kurt Kimmel, Mark Slezak, Gary Dabbagh, Takashi Chiba, Tsutomu Shimokawa

Proceedings Volume 5753, (2005) https://doi.org/10.1117/12.601621

KEYWORDS: Polymers, Lithography, Immersion lithography, Materials processing, Semiconducting wafers, Particles, Photoresist materials, Image processing, Photoresist processing, Scanners

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Showing 5 of 9 publications

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