The Edge Placement Error (EPE) is growing concerns due to the complexity increases of process variation as the design rule shrinkage of DRAM device. The EPE is a well-accepted metric which can be derived from CD, Overlay and LER measurements from more than patterning layers that concerned. Therefore, real time EPE measurement becomes a major factor to monitor and control the pattern fidelity. The pattern fidelity could be found from the edge placement measurement as a distance to design intent as possible without pattern defects. However, the traditional application of photolithography and etch biases according to a design rule or model for identifying pattern fidelity has inherent low TMU, multiple non consistence data sources and time-consuming off-line analysis. In previous works, we demonstrated the innovative e-Beam EPE metrology application using All-In-One (AIO) methodology to comply the required Total Measurement Uncertainty (TMU) and Time to Result (TTR) on the advanced DRAM nodes. AIO imaging and analysis methodology that deconvolute CD, overlay and relevant EPE metrics from a single see-through image is the most important differentiation for this EPE analysis approach. The in-cell direct EPE measurement with All-In-One (AIO) imaging and massive sampling demonstrates the better process controls and monitoring from the co-optimization of multiple control parameters and direct measurement of the yield relevant metrics. In this paper, we would like to show a couple of EPE monitoring use cases which shows good correlation to the final yield map through the massive and multi-layer measurements. Especially, it is expected that the EPE component which measures the edge-to-edge distance between different features of multi-layers can be a useful indicator for predicting yield along with CD and overlay. To investigate the local and random variabilities, which local stochastic effects are contained, we also studied the degree of yield prediction of the EPE component with increasing number of measurement sites in local area. It is proposed that using a large amount of measurement sites allows to improve the yield prediction accuracy to a certain extent, which means the local stochastic effects can be effectively analyzed with the use of massive metrology approach. In addition, from the prediction accuracy study using EPE model-based machine learning, we proved that the EPE is sufficiently sensitive indicator to capture potential yield-loss problems in normal wafer, as well. Therefore, in-line EPE monitoring using AIO metrology enables the root-cause analysis of patterning weak points and provides a better process monitoring/correction solution to enable faster advanced DRAM node development ramp and high-volume stability.
For advanced nodes, a robust metrology is required to estimate EPE and its contributors. Especially when moving to late process development steps (Ramp-Up and High Volume Manufacturing (HVM)) where inter and intra wafer variations are small but crucial. In this study, we used 8um by 8um SEM images to assess the benefit of large Field-of-View (LFOV) metrology. The result proves the capability of LFOV metrology in capturing not only intra-wafer EPE behavior and its sensitivity to minor variations but also the minor wafer-to-wafer (W2W) variations which is not possible using a small FOV (SFOV) metrology (0.5um by 0.5um) due to larger noise level.
As the semiconductor industry rapidly approaches the 3nm lithography node, on-product overlay (OPO) requirements have become tighter, which drives metrology performance enhancements to meet the reduction in overlay (OVL) residuals. The utilization of multiple measurement wavelengths in Imaging- Based Overlay (IBO) has increased in the past few years to meet these needs. Specifically, the color per layer (CPL) method allows for optimizing the OVL measurement conditions per layer, including focus, light, wavelength (WL), and polarization customization which enhance the metrology results. CPL is applicable for multiple technology segments (logic, foundry, DRAM, 3D NAND), relevant for different devices (DRAM high stack layers, NAND channel holes, etc.), and can work well for both thin and thick layers for standard and EUV lithography processes. In this paper, we will review the benefits of CPL for multiple DRAM and NAND critical layers. We will describe how CPL can contribute to measurement accuracy by quantifying the OVL residual reduction in comparison to single-wavelength (SWL) measurement conditions.
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