Ultraviolet nanoimprint lithography (NIL) is a simple contact process that is attractive and promising process for high pattern fidelity, without blurring effect due to light scattering or acid diffusion in the resist. Specifically, complicated 3D patterns, fine 2D patterns, and fine 1D patterns can be formed in fewer process steps compared to those for optical lithography. On the other hand, there are fewer adjustment knobs for process tuning in NIL; therefore, it is necessary to introduce design restrictions customized for NIL to improve the process margin. Since pattern transfer is performed through filling of a resist having a finite volume, a design constraint considering filling property is required to reduce defect density and improve throughput. In this study, two types of design constraints are examined to address the NIL process margin problem. One is a NIL alignment mark design that satisfies both signal strength and filling characteristics. The other is a combination of the pattern coverage rule with wafer topography that achieves good filling characteristics under various substrate unevenness conditions. Experiment results were interpolated with NIL process simulations and common areas under various conditions were extracted to identify the design rules for achieving large process margins. By using a design flow that considers these rules, we believe that high volume manufacturing (HVM) yields can be increased considerably by reducing yield issues and reducing redesign loops.
KEYWORDS: Directed self assembly, Image processing, Signal processing, Electron beam lithography, Lithography, Annealing, Thin films, Epitaxy, Data modeling, 3D modeling
Directed self-assembly (DSA) of block copolymers (BCPs) is a lithographic technique that is expected to be mutually complimentary with ArF immersion lithography, EUV lithography, electron beam direct writing, or nanoimprint for sub-15 nm line patterning and sub-20 nm contact hole patterning. Defect mitigation is the primary challenge behind the use of DSA lithography in practical applications in advanced semiconductor device manufacturing. Therefore, resolve this issue, defect dynamics needs to be clarified using in-situ measurements of self-assembling processes of BCPs in conjunction with modeling approaches.
In this work, the evolution of a surface morphology in self-assembling processes of BCPs during annealing was investigated using in-situ atomic force microscope (AFM).5 A JPK NanoWizard ULTRA Speed AFM (JPK Instruments AG) under AC mode (lock-in phase signal image) was employed to carry out in-situ measurements of self-assembling of symmetrical polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) thin films with a thickness of 40 nm, and a domain spacing 30 nm domain spacing (L0) of 30 nm on a 5 nm thick neutral layer (PS-r-PMMA) during the thermal annealing process starting from a disordered as-cast state. The COOrdinated Line epitaxy (COOL) process was applied to provide DSA line multiplication patterns as hybrid guide patterns which act as chemical and physical epitaxy process.
The in-situ observation approach of the surface morphology during micro-phase separation process revealed the defect generation and rectification processes in DSA thin films. A combination of the time development data in the in-situ AFM and grazing-incidence small-angle X-ray scattering (GI-SAXS) will also be discussed to develop a kinetic modeling for predicting dynamical changes in the three-dimensional nanostructures.
In this paper we will describe a self-consistent field theory simulation study on bridge defects in lamellae-forming diblock copolymers. Because the bridge defects are buried three-dimensional defects formed in the diblock copolymer film, it is difficult to observe and determine what causes them. To determine the cause of the bridge defects effectively, self-consistent field theory simulations were used. By reproducing structural characteristics of the bridge defects in the simulation, the cause of the bridge defects were clarified. Finally, we discussed ways to prevent the bridge defects.
Directed self-assembly (DSA) of block copolymers (BCPs) has been expected to become one of the most promising next generation lithography candidates for sub-15 nm line patterning and sub-20 nm contact hole patterning. In order to provide the DSA lithography to practical use in advanced semiconductor device manufacturing, defect mitigation in the DSA materials and processes is the primary challenge. We need to clarify the defect generation mechanism using in-situ measurement of self-assembling processes of BCPs in cooperation with modeling approaches to attain the DSA defect mitigation.
In this work, we thus employed in-situ atomic force microscope (AFM) and grazing-incidence small angle X-ray scattering (GI-SAXS) and investigated development of surface morphology as well as internal structure during annealing processes.
Figure 1 shows series of the AFM images of PMAPOSS-b-PTFEMA films during annealing processes. The images clearly show that vitrified sponge-like structure without long-range order in as-spun film transforms into lamellar structure and that the long range order of the lamellar structure increases with annealing temperature. It is well-known that ordering processes of BCPs from disordered state in bulk progress via nucleation and growth. In contrary to the case of bulk, the observed processes seem to be spinodal decomposition. This is because the structure in as-spun film is not the concentration fluctuation of disordered state but the vitrified sponge-like structure. The annealing processes induce order-order transition from non-equilibrium ordered-state to the lamellar structure. The surface tension assists the transition and directs the orientation.
Figure 2 shows scattering patterns of (a) vicinity of film top and (b) whole sample of the GI-SAXS. We can find vertically oriented lamellar structure in the vicinity of film top while horizontally oriented lamellar structures in the vicinity of film bottom, indicating that the GI-SAXS measurement can clarify the variation of the morphologies in depth direction and that the surface tension affects the orientation of the lamellar structure. Finally a combination of the time development data in the in-situ AFM and the GI-SAXS is used to develop a kinetic modeling for prediction of dynamical change in three-dimensional nano-structures.
A part of this work was funded by the New Energy and Industrial Technology Development Organization (NEDO) in Japan under the EIDEC project.
In this study, we investigated a directed self-assembly (DSA) flow that could include a non-periodic pattern (i.e., wide line) lying in between the periodic line/space patterns, in a relatively simple and inexpensive way. A symmetric poly(styrene-block-methyl methacrylate) (PS-b-PMMA) with the natural periodicity (L0) of 30 nm was employed here. Our DSA flow has two key features. First, we used a hybrid approach that combined chemoepitaxy and graphoepitaxy methods to generate PMMA-attractive pinning guide patterns directly from ArF resist. Second, we attempted to utilize both the perpendicular lamellae in the periodic regions and the horizontal lamellae on the non-periodic pattern as an etch template. The advantage of this process will be a reduction of the number of lithographic processes, whereas the challenge is how to control the mixed morphologies at the boundary between the periodic and non-periodic regions. Our preliminary results from simulations and experiments showed that, in order to generate the horizontal lamellae on the non-periodic pattern, the PS-b-PMMA thickness on top of the non-periodic guide pattern should roughly match to ~1 L0, and the width of the non-periodic pattern should be larger than ~3-4 L0. In addition, the space between the periodic and non-periodic regions was found to be critical and it should be basically equal to the space between the guiding pins in the periodic regions (~75 nm) to minimize the formation of fingerprint morphology at the boundaries.
Our target at EIDEC is to study the feasibility of directed self-assembly (DSA) technology for semiconductor device manufacturing through electrical yield verification by development of such as process, material, metrology, simulation and design for DSA. We previously developed a grapho/chemo-hybrid coordinated line epitaxial process for sub-15-nm line-and-space (L/S) patterning using polystyrene-block-poly(methyl methacrylate) lamellar block copolymers (BCPs)1– 3. Electrical yield verification results showed that a 30% open yield was successfully achieved with a metal wire line length of 700 μm 4. In the next stage of the evaluation, a sub-10-nm L/S DSA patterning process based on graphoepitaxial DSA of 20-nm lamellar period organic BCPs was developed based on neutral layer and guide space width optimization. At a 30-nm guide height, problems such as BCP overflow and DSA line shorts were observed after the dry development. At a 60-nm guide height, grid-like short defects were observed under dry development shallow etch conditions and sub-10-nm L/S patterns were formed under optimized etch conditions with a suitable BCP film thickness margin. The process performance was evaluated in terms of defects and critical dimension measurements using an electron beam inspection system and critical dimension-scanning electron microscope metrology. The main DSA defects were short defects, and the spatial roughness appeared to be caused by the periodic pitches of these short defects and the guide roughness. We successfully demonstrated the fabrication of sub-10-nm metal wires consists of L/S, pad, connect and cut patterns with controlled alignment and stack structure through lithography, etching and CMP process on a 300- mm wafer using the fully integrated DSA process and damascene processing.
Si-rich poly((polyhedral oligomeric silsesquioxane) methacrylate)-b-poly(trifluoroethyl methacrylate) (PMAPOSS-b- PTFEMA) was used to form 8-nm half-pitch line and space (L/S) pattern via grapho-epitaxy. Vertical alignment of the lamellae was achieved without using either a neutral layer or top-coating material. Because PMAPOSS-b-PTFEMA forms vertical lamellae on a variety of substrates, we used two types of physical guide structures for grapho-epitaxy; one was a substrate guide and the other was a guide with an embedded under layer. On the substrate guide structure, a fine L/S pattern was obtained with trench widths equal to 3–7 periods of the lamella spacing of the block copolymer, Lo. However, on the embedded under layer guide structure, L/S pattern was observed only with 3 Lo and 4 Lo in trench width. Cross-sectional transmission electron microscope images revealed that a thick PMAPOSS layer was formed under the PMAPOSS-b-PTFEMA L/S pattern. Pattern transfer of the PMAPOSS-b-PTFEMA L/S pattern was prevented by a thick PMAPOSS layer. To achieve pattern transfer to the under layer, optimization of the surface properties is necessary.
Directed self-assembly is a candidate process for sub-15-nm patterning applications. It will be necessary to develop the DSA process fully and consider process integration to adapt the DSA process for use in semiconductor manufacturing. We investigated the reactive ion etching (RIE) process for the fabrication of sub-10-nm metal wires using the DSA process and the process integration requirements for electrical yield verification. We evaluated the process using an organic high-chi block copolymer (BCP) with a lamellar structure. One critical issue during DSA pattern transfer involves the BCP bottom connection. The BCP bottom connections could be removed without BCP mask loss by using the optimum bias power and the optimum BCP film thickness. The sub-10-nm DSA line-and-space (L/S) patterns were successfully transferred to a SiO2 layer with sufficient film thickness for the fabrication of the metal wire. We also evaluated the overlay technique used in the process. The connect patterns and cut patterns were overlaid on 10-nm trenches fabricated by the DSA process.
The perpendicularly orientated lamellar structure of the self-organized diblock copolymer is an attractive template for sub-10-nm line-and-space pattern formation. We propose a method of evaluating the neutral layer (NL) whose performance has an important bearing on the perpendicular orientation of the lamellar structure. The random copolymer of methyl methacrylate and i-butyl POSS methacrylate (MAIBPOSS) has been investigated as an NL for a polymethylmethacrylate-b-polymethacrylethylPOSS (PMMA-b-PMAIBPOSS) lamellar structure. PMMA-b-PMAIBPOSS material has the potential to form sub-10 nm line-and-space pattern, in addition to high etch selectivity due to its POSS structure. Under the free surface, PMMA-b-PMAIBPOSS film on the random copolymer layer showed horizontal orientation. However, a half-pitch of a 7-nm finger pattern structure was observed by peeling off the horizontally oriented layer. The upper portion of the PMMA-b-PMAIBPOSS film was eliminated till proximity of the random copolymer layer by CF4 gas etching. From the result, it was revealed that the PMMA-r-PMAIBPOSS works as an NL. It was confirmed that the contact angle analysis using an appropriate polymer is a suitable method for evaluation of the surface energy performance of the copolymer with the attribute of high segregation energy.
In this study, half-pitch (HP) 15 nm line-and-space (L/S) metal wires were successfully fabricated and fully integrated on a 300 mm wafer by applying directed self-assembly (DSA) lithography and pattern transfer for semiconductor device manufacturing. In order to evaluate process performances of DSA, we developed a simple sub-15 nm L/S patterning process using polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) lamellar block copolymer (BCP), which utilizes trimming resist and shallow etching spin-on-glass (SOG) as pinning guide[1]-[4]. From the results of defect inspection after SOG etch using Electron Beam (EB) inspection system, defects were classified as typical DSA defects or defects relating to DSA pattern transfer. From the evaluation of DSA L/S pattern Critical Dimension (CD), roughness and local placement error using CD-SEM, it is considered that isolated PS lines are placed at the centerline between guides and that placement of paired PS lines depends on the guide width. The control of the guide resist CD is the key to local placement error and the paired lines adjacent to the guide shifted toward the outside (0.5 nm) along the centerline of the isolated line after SOG etch. We demonstrated fabrication of HP 15 nm metal wires in trenches formed by the DSA process with reactive ion etching (RIE), followed by metal chemical vapor deposition (CVD) and chemical mechanical polishing (CMP). By SEM observation of alignment errors between the trenches and connect spaces, overlay shift patterns (-4 nm) in guide lithography mask were fabricated without intra-wafer alignment errors.
Directed self-assembly (DSA) is one of the promising candidates for next-generation lithography. We developed a novel simple sub-15 nm line-and-space (L/S) patterning process, the “coordinated line epitaxy (COOL) process,” using grapho- and chemo-hybrid epitaxy. In this study we evaluate the DSA L/S pattern transfer margin. Since defect reduction is difficult in the case of the DSA pattern transfer process, there is a need to increase the pattern transfer margin. We also describe process integration for electrical yield verification.
We proposed a new concept of “defect-aware process margin.” Defect-aware process margin was evaluated by investigating the energy difference between the free-energy of the most stable state and that of the first metastable state. The energy difference is strongly related to the defect density in DSA process. As a result of our rigorous simulations, the process margin of the pinning layer width was found to be: (1) worse when the pinning layer affinity is too large, (2) better when the background affinity has the opposite sign of the pinning layer affinity, and (3) better when the top of the background layer is higher than that of the pinning layer by 0.1L0.
Mask-induced aberration, which causes the deterioration of pattern fidelity owing to the phase difference between the diffraction orders in sub-wavelength lithography conditions, is an intricate problem. To evaluate the extent of the effect computationally, a rigorous electromagnetic field solver is applied. Reduction in the computation time of full-3D calculation is desirable in order to calculate practical patterns of mask layout in short period of time. We propose a new approach based on the Constrained Interpolation Profile (CIP) scheme with Method of Characteristics (MoC) to achieve the reduction of computation time. The CIP scheme is characterized by high accuracy to maintain the phase of each propagating wave using spatial derivatives. Constrained interpolation with derivatives is efficient for reducing the number of cells in the spatial domain because the requirement for keeping the phase accuracy of wavefront is relaxed. Non-uniform meshing also reduces the amount of computation time. The CIP scheme connects the mask topography simulation using non-uniform mesh to the traditional imaging algorithm smoothly. In this paper, we discuss the accuracy of CIP-based Mask3D simulation and the applicability to lithography issues.
Dissipative particle dynamics (DPD) simulations are utilized to optimize contact hole shrink process using
graphoepitaxial directed self-assembly (DSA). In this work, poly (styrene-block-methyl methacrylate) (PS-b-PMMA)
was employed. In the contact hole shrink process, PS residual layer was formed on the bottom floor of the hole type prepattern.
To realize reliable contact hole shrink process, minimization of the thickness of PS residual layer was one of the
key issues. It was found that the minimization of the thickness of the PS residual layer and optimization of threedimensional
configuration of the PMMA domain was trade-off relationship. By using DPD simulations, the parameters
were successfully optimized to achieve residual layer free contact hole shrink of DSA lithography.
Directed self-assembly lithography (DSAL), which combines self-assembling materials and a lithographically
defined prepattern, is a potential candidate to extend optical lithography beyond 22 nm. To take full
advantage of DSAL requires diminishing not only systematic error modes but also random error modes by
carefully designing a lithographically defined prepattern and precisely adjusting process conditions. To
accomplish this with satisfactory accuracy, we have proposed a novel method to evaluate DSAL error modes
based on simulations using dissipative particle dynamics (DPD). We have found that we can estimate not only
systematic errors but also random errors qualitatively by simulations.
We have developed the comprehensive sub-resolution assist features (SRAFs) generation method based upon the
modulation of the coherence map. The method has broken through the trade-off relation between processing time and
accuracy of the SRAF generation. We have applied this method to a real device layout and the average of Process
Variation band width (PV band width) has improved to 40% without any processing time loss.
Lithography compliance check (LCC), which is verification of layouts using lithography simulation, is an essential step
under the current low k1 lithography condition. In general, LCC starts from primitive cell block level and checks bigger
block level in the final stage. However, hotspots may be found by chip level LCC although LCC does not find any
hotspots in a primitive cell block check, because conventional LCC for primitive cell blocks cannot consider the
influence of the optical proximity effect from neighboring cell structures at the chip level.
This paper proposes a new verification method in order to resolve this issue. It consists of three steps. The first step is the
same as the conventional method; run LCC and judge if there are hotspots, which need to be fixed. The second step is
judge if there are warmspots, which represent the pattern structures with borderline litho margin, and if warmspots are
found, add a pattern that makes process margin worst. The third step is to fix the hotspots changing from warmspots by
adding the worst pattern. Based on this method, primitive cell block LCC can guarantee that there are no hotspots at the
chip level without chip level LCC. We discuss the detail of process flow of this verification method and validate the
effect of this method.
We have studied the parameter setting dependence on the OPC TAT and OPC accuracy. We have found that we can
save OPC TAT with sufficient accuracy by optimizing the optical diameter, fringe length, and the kernel counts in
optical simulations of OPC. The optical diameter should be set to the optimal value depending on its mask design
regularity. In the kernel-based optical simulations, the residual error is found to drop suddenly at the critical kernel count.
This critical kernel count is found to be almost independent of the optical diameter, aberrations, and resist stack
structures. On the other hand, it is clarified that the critical kernel count is strongly correlated with the coherence factor
of the illuminations. Using this critical kernel count, we can obtain the image intensities with sufficient accuracy. We
propose a method to determine fringe length by analyzing the characteristics of the optical kernels that are independent
of the mask layouts.
Mask specifications of the pitch splitting type double patterning for 22nm node and beyond in logic
devices have been discussed. The influences of the mask CD error and the mask induced overlay
error on wafer CD have been investigated in both cases of bright field and dark filed. The
specification for intra-layer overlay alignment is much smaller than inter-layer one. The specification
of mask CD uniformity for dark is more challenging. In order to overcome the technology gap
between single patterning and double patterning, many things will have to be improved.
We have designed the lithography process for 32nm node logic devices under the 1.3NA single exposure
conditions. The simulation and experimental results indicate that the minimum pitches should be
determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated
feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um2 area is clearly
resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability.
There is no immersion induced defects.
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