The recent explosive compute growth, mainly fueled by the boost of artificial intelligence (AI) and deep neural networks (DNNs), is currently instigating the demand for a novel computing paradigm that can overcome the insurmountable barriers imposed by conventional electronic computing architectures. Photonic neural networks (PNNs) implemented on silicon photonic integration platforms stand out as a promising candidate to endow neural network (NN) hardware, offering the potential for energy efficient and ultra-fast computations through the utilization of the unique primitives of light i.e. THz bandwidth, low-power and low-latency. Thus far, several demonstrations have revealed the huge potential of PNNs in performing both linear and non-linear NN operations at unparalleled speed and energy consumption metrics. Transforming this potential into a tangible reality for Deep Learning (DL) applications requires, however, a deep understanding of the basic PNN principles, requirements and challenges across all constituent architectural, technological and training aspects. In this paper we review the state-of-the-art photonic linear processors and project their challenges and solutions for future photonic-assisted machine learning engines. Additionally, recent experimental results using SiGe EAMs in a Xbar layout are presented, validating light's credentials to perform ultra-fast linear operations with unparalleled accuracy. Finally, we provide an holistic overview of the optics-informed NN training framework that incorporates the physical properties of photonic building blocks into the training process in order to improve the NN classification accuracy and effectively elevate neuromorphic photonic hardware into high-performance DL computational settings.
Photonic Neural Networks (PNNs) implemented on silicon photonic (SiPho) platforms stand out as a promising candidate to endow neural network hardware, offering the potential for energy efficient and ultra-fast computations through exploiting the unique primitives of light i.e., THz bandwidth, low-power and low-latency. In this paper, we review the state-of-the-art photonic linear processors discuss their challenges and propose solutions for future photonic-assisted machine learning engines. Additionally, we will present experimental results on the recently introduced SiPho 4x4 coherent crossbar (Xbar) architecture, that migrates from existing Singular Value Decomposition (SVD)-based schemes while offering single time-step programming complexity. The Xbar architecture utilizes silicon germanium (SiGe) Electro-Absorption Modulators (EAMs) as its computing cells and Thermo-Optic (TO) Phase Shifters (PS) for providing the sign information at every weight matrix node. Towards experimentally evaluating our Xbar architecture, we performed 10,024 arbitrary linear transformations over the SiPho processor, with the respective fidelity values converging to 100%. Followingly, we focus on the execution of the non-linear part of the NN by demonstrating a programmable analog optoelectronic circuit that can be configured to provide a plethora of non-linear activation functions, including tanh, sigmoid, ReLU and inverted ReLU at 2 GHz update rate. Finally, we provide a holistic overview on optics-informed neural networks towards improving the classification accuracy and performance of optics-specific Deep Learning (DL) computational tasks by leveraging the synergy of optical physics and DL.
Rapid developments in computer science have led to the increasing demand for efficient computing systems. Linear photonic systems rose as a favorable candidate for workload-demanding architectures, due to their small footprint and low energy consumption. Mach Zehnder Interferometers (MZI) serve as the foundational building block for several photonic circuits, and have been widely used as modulators, switches and variable power splitters. However, combining MZIs for realizing multiport splitters remains a challenge, since the exponential increase in the number of devices and the consequential increase in losses is limiting the performance of the MZI based multiport device. To overcome such limitations, incorporating alternative and low loss integration platforms combined with a generalized design of the MZI could allow the realization of a robust variable power splitter. In this work, we present for the first time a 4×4 Generalized Mach Zehnder Interferometer (GMZI) incorporated on a Si3N4 photonic integration platform and we experimentally demonstrate its operation as a variable power splitter. We developed an analytical model to describe the operation of the 4×4 GMZI, allowing us to evaluate the impact of several parameters to the overall performance of the device and investigate the device’s tolerance to fabrication imperfections and design alternations. Its experimental evaluation as a variable power splitter reveals a controlled imbalance that ranges up to 10 dB in multiple output ports of the device, validating the theoretically derived principles of operation.
The explosive volume growth of deep-learning (DL) applications has triggered an era in computing, with neuromorphic photonic platforms promising to merge ultra-high speed and energy efficiency credentials with the brain-inspired computing primitives. The transfer of deep neural networks (DNNs) onto silicon photonic (SiPho) architectures requires, however, an analog computing engine that can perform tiled matrix multiplication (TMM) at line rate to support DL applications with a large number of trainable parameters, similar to the approach followed by state-of-the-art electronic graphics processing units. Herein, we demonstrate an analog SiPho computing engine that relies on a coherent architecture and can perform optical TMM at the record-high speed of 50 GHz. Its potential to support DL applications, where the number of trainable parameters exceeds the available hardware dimensions, is highlighted through a photonic DNN that can reliably detect distributed denial-of-service attacks within a data center with a Cohen’s kappa score-based accuracy of 0.636.
The emergence of demanding machine learning and AI workloads in modern computational systems and Data Centers (DC) has fueled a drive towards custom hardware, designed to accelerate Multiply-Accumulate (MAC) operations. In this context, neuromorphic photonics have recently attracted attention as a promising technological candidate, that can transfer photonics low-power, high bandwidth credentials in neuromorphic hardware implementations. However, the deployment of such systems necessitates progress in both the underlying constituent building blocks as well as the development of deep learning training models that can take into account the physical properties of the employed photonic components and compensate for their non-ideal performance. Herein, we present an overview of our progress in photonic neuromorphic computing based on coherent layouts, that exploits the phase of the light traversing the photonic circuitry both for sign representation and matrix manipulation. Our approach breaks-through the direct trade-off of insertion loss and modulation bandwidth of State-Of-The-Art coherent architectures and allows high-speed operation in reasonable energy envelopes. We present a silicon-integrated coherent linear neuron (COLN) that relies on electro-absorption modulators (EAM) both for its on-chip data generation and weighting, demonstrating a record-high 32 GMAC/sec/axon compute linerate and an experimentally obtained accuracy of 95.91% in the MNIST classification task. Moreover, we present our progress on component specific neuromorphic circuitry training, considering both the photonic link thermal noise and its channel response. Finally, we present our roadmap on scaling our architecture using a novel optical crossbar design towards a 32×32 layout that can offer >;32 GMAC/sec/axon computational power in ~0.09 pJ/MAC.
The ever-increasing energy consumption of Data Centers (DC), along with the significant waste of resources that is observed in traditional DCs, have forced DC operators to invest in solutions that will considerably improve energy efficiency. In this context, Rack- and board-scale resource disaggregation is under heavy research, as a groundbreaking innovation that could amortize the energy and cost impact caused by the vast diversity in resource demand of emerging DC workloads. However disaggregation, by breaking apart the critical CPU-to-memory path, introduces a challenging set of requirements in the underlying network infrastructure, that has to support low-latency and high-throughput communication for a high number of nodes.
In this paper we present our recent work on optical interconnects towards enabling resource disaggregation both on Rack-level as well as on board-level. To this end, we have demonstrated the Hipoλaos architecture that can efficiently integrate Spanke-based switching with AWGR-based wavelength routing and optical feedforward buffering into highport switch layouts. The proof-of-concept Hipoλaos prototype, based on the 1024-port layout, provide latency performance of 456ns, while system level evaluations reveal sub-μs latency performance for a variety of synthetic traffic profiles. Moving towards high-capacity board-level interconnects, we present the latest achievements realized within the context of H2020-STREAMS project, where single-mode optical PCBs hosting Si-based routing modules and mid-board optics are exploited towards a massive any-to-any, buffer-less, collision-less and extremely low latency routing platform with 25.6Tb/s throughput. Finally, we combine the Hipolaos and STREAMS architectures in a dual-layer switching scheme and evaluate its performance via system-level simulations.
The rapid increase of bandwidth requirements across the entire hierarchy of Data Center (DC) networks, ranging from chip-to-chip, board-to-board up to rack-to-rack communications, puts strenuous requirements in the underlying network infrastructure that has to offer high-bandwidth and low-latency interconnection under a low-energy and low-cost envelope. Arrayed Waveguide Grating Router (AWGR)-based optical interconnections have emerged as a powerful architectural framework that can overcome the currently deployed electrical interconnect bottlenecks leveraging the wavelength division multiplexing (WDM) and the cyclic routing properties of AWGRs to offer one-hop, all-to-all communication when employed as N×N routers. However, the majority of previous silicon (Si)-based integrated AWGR demonstrations has either targeted C-band operation, despite the dominance of the O-band spectral region in the DC interconnection domain, or offered coarse-WDM (CWDM) functionality and, as such, were limited in terms of AWGR port count. In this article, we present for the first time to our knowledge, a Dense-WDM (DWDM) 16×16 Si-photonic cyclic-frequency AWGR device targeting O-band routing applications. The fabricated AWGR device features a channel spacing of 1.063 nm (189 GHz), a free spectral range of 17.8 nm (3.15 THz) and a 3-dB bandwidth of 0.655 nm (116 GHz). Its proper cyclic frequency operation was experimentally verified for all 16 channels with channel peak insertion loss values in the range of 3.9 dB to 8.37 dB, yielding a channel loss non-uniformity of 4.47 dB. Its compact footprint of 0.27×0.71 mm2 and low crosstalk of 21.65 dB highlight its potential for employment in future AWGR-based interconnection schemes.
KEYWORDS: Eye, Signal attenuation, Signal processing, Data conversion, Modulators, Optical filters, Bandpass filters, Amplitude modulation, Information science, Network architectures
The 5G-induced paradigm shift from traditional macro-cell networks towards ultra-dense deployment of small cells, imposes stringent bandwidth and latency requirements in the underlying network infrastructure. While state of the art TDM-PON e.g. 10G-EPON, have already transformed the fronthaul networks from circuit switched point-to-point links into packet based architectures of shared point-to-multipoint links, the 5G Ethernet-based fronthaul brings new requirements in terms of latency for an inherently bursty traffic. This is expected to promote the deployment of a whole new class of optical devices that can perform with burst-mode traffic while realizing routing functionalities at a low-latency and energy envelope, avoiding in this way the latency burden associated with a complete optoelectronic Ethernet routing process and acting as a fast optical gateway for ultra-low latency requiring signals. Wavelength conversion can offer a reliable option for ultra-fast routing in access and fronthaul networks, provided, however, that it can at the same time offer both packet power-level equalization to account for differences in optical path losses and comply with the typical, in optical fronthauling, NRZ format. In this paper, we demonstrate an optical Burst-Mode Wavelength Converter using a Differentially-Biased SOA-MZI that operates in the deeply saturated regime to provide optical output power equalization for different input signal powers. The device has been experimentally validated for 10Gb/s NRZ optical packets, providing error-free operation for an input packet peak-power dynamic range of more than 9dB.
KEYWORDS: Switches, Optical switching, Field programmable gate arrays, Data centers, Switching, Computer architecture, Signal processing, Modulation, Device simulation, Data conversion
Disaggregated Data Centers (DCs) have emerged as a powerful architectural framework towards increasing resource utilization and system power efficiency, requiring, however, a networking infrastructure that can ensure low-latency and high-bandwidth connectivity between a high-number of interconnected nodes. This reality has been the driving force towards high-port count and low-latency optical switching platforms, with recent efforts concluding that the use of distributed control architectures as offered by Broadcast-and-Select (BS) layouts can lead to sub-μsec latencies. However, almost all high-port count optical switch designs proposed so far rely either on electronic buffering and associated SerDes circuitry for resolving contention or on buffer-less designs with packet drop and re-transmit procedures, unavoidably increasing latency or limiting throughput. In this article, we demonstrate a 256x256 optical switch architecture for disaggregated DCs that employs small-size optical delay line buffering in a distributed control scheme, exploiting FPGA-based header processing over a hybrid BS/Wavelength routing topology that is implemented by a 16x16 BS design and a 16x16 AWGR. Simulation-based performance analysis reveals that even the use of a 2- packet optical buffer can yield <620nsec latency with >85% throughput for up to 100% loads. The switch has been experimentally validated with 10Gb/s optical data packets using 1:16 optical splitting and a SOA-MZI wavelength converter (WC) along with fiber delay lines for the 2-packet buffer implementation at every BS outgoing port, followed by an additional SOA-MZI tunable WC and the 16x16 AWGR. Error-free performance in all different switch input/output combinations has been obtained with a power penalty of <2.5dB.
The urgent need for high-bandwidth and high-port connectivity in Data Centers has boosted the deployment of optoelectronic packet switches towards bringing high data-rate optics closer to the ASIC, realizing optical transceiver functions directly at the ASIC package for high-rate, low-energy and low-latency interconnects. Even though optics can offer a broad range of low-energy integrated switch fabrics for replacing electronic switches and seamlessly interface with the optical I/Os, the use of energy- and latency-consuming electronic SerDes continues to be a necessity, mainly dictated by the absence of integrated and reliable optical buffering solutions. SerDes undertakes the role of optimally synergizing the lower-speed electronic buffers with the incoming and outgoing optical streams, suggesting that a SerDes-released chip-scale optical switch fabric can be only realized in case all necessary functions including contention resolution and switching can be implemented on a common photonic integration platform. In this paper, we demonstrate experimentally a hybrid Broadcast-and-Select (BS) / wavelength routed optical switch that performs both the optical buffering and switching functions with μm-scale Silicon-integrated building blocks. Optical buffering is carried out in a silicon-integrated variable delay line bank with a record-high on-chip delay/footprint efficiency of 2.6ns/mm2 and up to 17.2 nsec delay capability, while switching is executed via a BS design and a silicon-integrated echelle grating, assisted by SOA-MZI wavelength conversion stages and controlled by a FPGA header processing module. The switch has been experimentally validated in a 3x3 arrangement with 10Gb/s NRZ optical data packets, demonstrating error-free switching operation with a power penalty of <5dB.
Programmable switching nodes supporting Software-Defined Networking (SDN) over optical interconnecting technologies arise as a key enabling technology for future disaggregated Data Center (DC) environments. The SDNenabling roadmap of intra-DC optical solutions is already a reality for rack-to-rack interconnects, with recent research reporting on interesting applications of programmable silicon photonic switching fabrics addressing board-to-board and even on-board applications. In this perspective, simplified information addressing schemes like Bloom filter (BF)-based labels emerge as a highly promising solution for ensuring rapid switch reconfiguration, following quickly the changes enforced in network size, network topology or even in content location. The benefits of BF-based forwarding have been so far successfully demonstrated in the Information-Centric Network (ICN) paradigm, while theoretical studies have also revealed the energy consumption and speed advantages when applied in DCs. In this paper we present for the first time a programmable 4x4 Silicon Photonic switch that supports SDN through the use of BF-labeled router ports. Our scheme significantly simplifies packet forwarding as it negates the need for large forwarding tables, allowing for its remote control through modifications in the assigned BF labels. We demonstrate 1x4 switch operation controlling the Si-Pho switch by a Stratix V FPGA module, which is responsible for processing the packet ID and correlating its destination with the appropriate BF-labeled outgoing port. DAC- and amplifier-less control of the carrier-injection Si-Pho switches is demonstrated, revealing successful switching of 10Gb/s data packets with BF-based forwarding information changes taking place at a time-scale that equals the duration of four consecutive packets.
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