KEYWORDS: Semiconductor manufacturing, Inspection, Image classification, Scanning electron microscopy, Deep learning, Semiconductors, Classification systems
The semiconductor manufacturing process is becoming more complex and time-consuming due to smaller design rules and denser patterns, which inevitably leads to an increase in the number and types of defects. In the past, considerable efforts have been made to classify defects, and this has been implemented at the equipment level. However, in order to enhance the efficiency and productivity of semiconductor process development by automatically classifying random, systematic, and parametric defects according to various process schemes and structures, there is a need for a deep learning-based automatic defect classification technique with a higher degree of freedom and utilization. In this study, we used not only scanning electron microscope images, which have been actively studied, but also optical inspection images at various scales. Deep learning algorithms were evaluated for various layers of memory devices to select the optimal algorithm for each layer, and an accuracy of 94% or more was achieved, even with a small sample size (under 1000), which is critical in the R&D stage. It is expected that this technique will be able to spread and be applied to more diverse layers in the future. By providing faster and more diverse classifications of defects in semiconductor manufacturing processes and ensuring higher consistency through continuous sample size expansion, it is anticipated that this technique will contribute to shortening the development period and improving yield.
In order to minimize wafer loss and increase productivity, it is important to predict the wafer yield drop caused by defects in early manufacturing stage. In conventional yield prediction method, the chip failure was manually checked using images sampled by defect inspection. However, it is insufficient to predict yield accurately since the prediction was performed with only a few sampled defect images. Furthermore, the kill-ratio per defect was not estimated properly because the electrical properties were not considered in predicting a failure such as short or open. In this paper, we propose a new yield prediction method using defect and layout information with the following two characteristics. We tried to overcome the existing sampling limitations by using the defect inspection raw data that contains the coordinates and size information of all defects. In addition, we matched the electrical signal information of the layout pattern with silicon directly and then calculated the kill ratio per defect. The kill ratio per defect has doubled from 30% to 70% applied to sub-20nm Emerging memory devices. And we have confirmed that the yield prediction gap, which is the difference between the predicted yield and the actual yield, decreases from 31% to 8%. It is expected to reduce wafer loss about 10% in Emerging memory devices and same improvement will occur in other products such as DRAM, FLASH, and LOGIC devices by applying this sophisticated methodology.
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