In this paper, a high-speed CMOS image sensor having a new architecture and a new operating principle has been
developed. The image sensor achieves both the continuous capturing and the burst capturing by a single chip, and has
low power consumption, low heat generation, high sensitivity and high S/N ratio. This image sensor consist of mainly
four blocks, two dimensional pixel array of 4-transister CMOS active pixel, analog memory arrays connected with each
pixel output line independently to the pixel array, scanning circuits and multiple number of output amplifiers. A
prototype image sensor was fabricated using a 0.18μm 2-Poly 3-Metal CMOS technology with the die size of 5550 μmH
x 4575 μmV, the pixel size of 48 μmH x 48 μmV, the number of pixels of 72H x 32V, the number of analog memories of
104 memories per pixel and the 6 parallel horizontal output circuits and output amplifiers. The aperture ratio is 35% and
the conversion gain is 60 μV/e-(input referred). It has been confirmed that this image sensor achieves 10,000,000 fps
during burst capturing mode and 10,000 fps during the continuous capturing mode through the image capture
experiments of high speed phenomena such as rotating object and discharge phenomenon.
Operation methods for high frame rate, linear response, wide dynamic range (DR) and high SNR in a CMOS image sensor are discussed. The high frame rate operation is realized by the optimum design of the floating diffusion capacitor, the lateral overflow integration capacitor, the column integration capacitor and the integration periods of multiple voltage and current readout operations. The color CMOS image sensor which consists of the 1/3-inch, 800H × 600V pixels and 5.6-μm pixel pitch with a buried pinned-photodiode, a transfer switch, a reset switch, a lateral overflow switch, a lateral overflow integration capacitor, a photocurrent readout switch, a source follower transistor and a pixel select switch in each pixel has been fabricated by 0.18-μm 2P3M CMOS technology. The image sensor operates the total frame rate of 13-fps with three-time voltage readout operations and one current readout operation and have realized full linear photoelectric conversion responses, over 20-dB SNR for the image of the 18-% gray card at all integration operation switching points and the over 200-dB DR.
KEYWORDS: CMOS sensors, Front end of line, Photodiodes, Sensors, Image quality, Image sensors, Interference (communication), Signal to noise ratio, Back end of line, Switches
A temperature-resistant 1/3 inch SVGA (800×600 pixels) 5.6 μm pixel pitch wide-dynamic-range (WDR) CMOS image
sensor has been developed using a lateral-over-flow-integration-capacitor (LOFIC) in a pixel. The sensor chips are
fabricated through 0.18 μm 2P3M process with totally optimized front-end-of-line (FEOL) & back-end-of-line (BEOL)
for a lower dark current. By implementing a low electrical field potential design for photodiodes, reducing damages,
recovering crystal defects and terminating interface states in the FEOL+BEOL, the dark current is improved to 12 e-
/pixel-sec at 60 deg.C with 50% reduction from the previous very-low-dark-current (VLDC) FEOL and its contribution to the temporal noise is improved. Furthermore, design optimizations of the readout circuits, especially a signal-and noise-hold circuit and a programmable-gain-amplifier (PGA) are also implemented. The measured temporal noise is 2.4 e-rms at 60 fps (:36 MHz operation). The dynamic-range (DR) is extended to 100 dB with 237 ke- full well capacity. In order to secure the temperature-resistance, the sensor chip also receives both an inorganic cap onto micro lens and a metal hermetic seal package assembly. Image samples at low & high temperatures show significant improvement in image qualities.
A high sensitivity and high full well capacity CMOS image sensor using active pixel readout feedback operation with positions of pixel select switch, operation timings and initial bias conditions has been reported. 1/3-inch 5.6-μm pixel pitch 800(H) x 600(V) color CMOS image sensors with the switch X set on or under the pixel SF have been fabricated by a 0.18-μm 2-Poly 3-Metal CMOS technology. The comparison of the active pixel readout feedback operation between two CMOS image sensors, which only have the deference of the switch X's position, has performed. As to the result, the switch X set on the pixel SF is favor for the active pixel readout feedback operation to improve the readout gain and the S/N ratio. This CMOS image sensor achieves high readout gain, high conversion gain, low input-referred noise and high full well capacity by the active pixel readout feedback operation.
It is indispensable for high quality image sensors to have performances of high sensitivity, low noise, high full well capacity and good linear response. The CMOS image sensor with the lateral overflow integration capacitor (LOFIC) has been accomplishing these performances because of its wide dynamic range capability in one exposure. Recently, we have improved the SNR of the LOFIC CMOS image sensor and achieved the number of input-referred noise electrons of 2 e- or below without any column amplifier circuits by increasing the photo-electric conversion gain at the floating diffusion (FD) in pixel as keeping low dark current, good uniformity and high well capacity. It is clear that the relation among the conversion gain, the SNR and the full well capacity decides the optimum design for the FD capacitance and the LOFIC to realize a high quality image sensor. In this paper, the optimum design method of the LOFIC CMOS image sensor for high sensitivity, low noise and high full well capacity is discussed through theoretical analysis and experiments by using the fabricated LOFIC CMOS image sensor.
A temperature resistant wide dynamic range (WDR) CMOS image sensor has been developed using the very low dark current front-end of line (VLDC FEOL) and the metal hermetic seal ceramic leadless chip carrier (CLCC) package suppressing the degradation of the spectra response of the on-chip micro lens and color filter (OCML/OCCF). A 1/4 inch VGA 5.6 &mgr;m pixel pitch WDR CMOS image sensor has been fabricated through 0.18 &mgr;m 2P3M process with the VLDC FEOL which contains the pinned photodiode with less electrical fields, the less plasma etching damages, the transfer gate with the suppressed current at Si-SiO2 interface and the furnace temperature process for the re-crystallization. The sensor chips with the conventional OCML/OCCF assembled into the metal hermetic seal package by the low residual oxygen vacuum welding machine has finally received the thermal stress test (150 deg.C/500 hours). The dark current is 350 pA/cm2 at 85 deg.C (50 pA/cm2 at 60 deg.C). No degradation of the spectra response in any of R/G/B pixels is observed after the thermal stress test. It is found that the thermal decomposition of the OCML/OCCF (phenol resin) is not caused easily in nitrogen with the low residual oxygen concentration. The sample images captured by the WDR CMOS image sensor assembled camera keep good quality up to 85 deg.C.
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